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1 parent 6e96cbe commit d4e2de8Copy full SHA for d4e2de8
fpga/io/acia/vhdl_source/acia6551.vhd
@@ -194,7 +194,7 @@ begin
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tx_pending <= '1';
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tx_presc <= "111";
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-- For receive, DTR should be active
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- elsif dtr = '1' and rx_head /= rx_tail and b_pending = '0' and rx_presc = "000" then
+ elsif rx_full = '0' and dtr = '1' and rx_head /= rx_tail and b_pending = '0' and rx_presc = "000" then
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b_address <= '1' & rx_tail;
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b_en <= '1';
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b_pending <= '1';
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