Various small improvements

Author: mrcmry

source/SpinalHDL/Libraries/Pipeline/introduction.rst

@@ -186,13 +186,13 @@ You can access its arbitration via :
      - Description
    * - ``node.valid``
      - RW
-     - Is the signal which specifies if a transaction is present on the node. It is driven by the upstream. Once asserted, it must only be de-asserted the cycle after which either both valid and ready or node.cancel are high. valid must not depend on ready.
+     - Is the signal which specifies if a transaction is present on the node. It is driven by the upstream. Once asserted, it must only be de-asserted the cycle after which either both ``valid`` and ``ready`` or ``node.cancel`` are high. ``valid`` must not depend on ``ready``.
    * - ``node.ready``
      - RW
-     - Is the signal which specifies if the node's transaction can proceed downstream. It is driven by the downstream to create backpressure. The signal has no meaning when there is no transaction (node.valid being deasserted)
+     - Is the signal which specifies if the node's transaction can proceed downstream. It is driven by the downstream to create backpressure. The signal has no meaning when there is no transaction (``node.valid`` being deasserted).
    * - ``node.cancel``
      - RW
-     - Is the signal which specifies if the node's transaction in being canceled from the pipeline. It is driven by the downstream. The signal has no meaning when there is no transaction (node.valid being deasserted)
+     - Is the signal which specifies if the node's transaction in being canceled from the pipeline. It is driven by the downstream. The signal has no meaning when there is no transaction (``node.valid`` being deasserted)
    * - ``node.isValid``
      - RO
      - ``node.valid``'s read only accessor
@@ -204,15 +204,15 @@ You can access its arbitration via :
      - ``node.cancel``'s read only accessor
    * - ``node.isFiring``
      - RO
-     - True when the node transaction is successfully moving further (valid && ready && !cancel). Useful to commit state changes.
+     - ``True`` when the node transaction is successfully moving further (``valid && ready && !cancel``). Useful to commit state changes.
    * - ``node.isMoving``
      - RO
-     - True when the node transaction will not be present anymore on the node (starting from the next cycle),
+     - ``True`` when the node transaction will not be present anymore on the node (starting from the next cycle),
        either because downstream is ready to take the transaction,
-       or because the transaction is canceled from the pipeline. (``valid && (ready || cancel)``). Useful to "reset" states.
+       or because the transaction is canceled from the pipeline (``valid && (ready || cancel)``). Useful to "reset" states.
    * - ``node.isCanceling``
      - RO
-     - True when the node transaction is being canceled. Meaning that it will not appear anywhere in the pipeline in future cycles.
+     - True when the node transaction is being cleaned up. Meaning that it will not appear anywhere in the pipeline in future cycles. It is equivalent to ``isValid && isCancel``.
 
 Note that the ``node.valid``/``node.ready`` signals follows the same conventions than 
 the :doc:`../stream`'s ones .

source/SpinalHDL/Libraries/stream.rst

@@ -113,6 +113,10 @@ Functions
      - Return True when a transaction is stall on the bus (valid && ! ready)
      - Bool
      - 
+   * - x.isFree
+     - Return True when the bus isn't stuck with a transaction (!isStall)
+     - Bool
+     -
    * - x.queue(size:Int)
      - Return a Stream connected to x through a FIFO
      - Stream[T]
@@ -219,20 +223,47 @@ On each stream you can call the .queue(size) to get a buffered stream. But you c
    myFifo.io.push << streamA
    myFifo.io.pop  >> streamB
 
+
+Mandatory parameters:
+
 .. list-table::
    :header-rows: 1
    :widths: 1 1 2
 
-   * - parameter name
+   * - Name
      - Type
      - Description
    * - dataType
      - T
      - Payload data type
    * - depth
      - Int
-     - Size of the memory used to store elements
+     - Number of element stored in the fifo, Note that if ``withAsyncRead==false``, then one extra transaction can be stored.
+    
+Optional parameters:
 
+.. list-table::
+   :header-rows: 1
+   :widths: 1 1 2
+
+   * - Name
+     - Default
+     - Description
+   * - withAsyncRead
+     - ``false``
+     - Read the memory using asynchronous read port (ex distributed ram). If false, add 1 cycle latency.
+   * - withBypass
+     - ``false``
+     - Bypass the push port to the pop port when the fifo is empty.If false, add  1 cycle latency. Only available if ``withAsyncRead == true``.
+   * - forFMax
+     - ``false``
+     - Tune the design to get the maximal clock frequency.
+   * - useVec
+     - ``false``
+     - Use an ``Vec`` of register instead of a Mem to store the content
+   * - initPayload
+     - ``None``
+     - A ``=> Option[T]`` function that return a value to init the  ``Vec`` register, only meaningful when ``useVec == true``
 
 .. list-table::
    :header-rows: 1
@@ -420,10 +451,10 @@ When you have multiple Streams and you want to arbitrate them to drive a single
 .. code-block:: scala
 
    val streamA, streamB, streamC = Stream(Bits(8 bits))
-   val arbitredABC = StreamArbiterFactory.roundRobin.onArgs(streamA, streamB, streamC)
+   val arbiteredABC = StreamArbiterFactory.roundRobin.onArgs(streamA, streamB, streamC)
 
    val streamD, streamE, streamF = Stream(Bits(8 bits))
-   val arbitredDEF = StreamArbiterFactory.lowerFirst.noLock.onArgs(streamD, streamE, streamF)
+   val arbiteredDEF = StreamArbiterFactory.lowerFirst.noLock.onArgs(streamD, streamE, streamF)
 
 .. list-table::
    :header-rows: 1
@@ -490,7 +521,7 @@ all output streams have processed each item regardlessly.
 .. code-block:: scala
 
    val inputStream = Stream(Bits(8 bits))
-   val (outputstream1, outputstream2) = StreamFork2(inputStream, synchronous=false)
+   val (outputStream1, outputStream2) = StreamFork2(inputStream, synchronous=false)
 
 or
 
@@ -558,11 +589,16 @@ The ``count`` is captured and registered each time inputStream fires for an indi
    val extender = StreamTransactionExtender(inputStream, outputStream, count) {
       // id, is the 0-based index of total output transfers so far in the current input transaction.
       // last, is the last transfer indication, same as the last signal for extender.
-      // the returned payload is allowed to be modified only based on id and last signals, other translation should be done outside of this.
+      // the returned payload is allowed to be modified only based on id and last signals, other
+      // translation should be done outside of this.
        (id, payload, last) => payload
    }
 
-This ``extender`` provides several status signals, such as ``working``, ``last``, ``done`` where ``working`` means there is one input transfer accepted and in-progress, ``last`` indicates the last output transfer is prepared and waiting to complete, ``done`` become valid represents the last output transfer is fireing and making the current input transaction process complete and ready to start another transaction.
+This ``extender`` provides several status signals, such as ``working``, ``last``, ``done`` where
+``working`` means there is one input transfer accepted and in-progress, ``last`` indicates the last
+output transfer is prepared and waiting to complete, ``done`` become valid represents the last
+output transfer is firing and making the current input transaction process complete and ready to
+start another transaction.
 
 .. wavedrom::
 

source/SpinalHDL/Structuring/clock_domain.rst

@@ -40,23 +40,25 @@ This definition takes five parameters:
      - Description
      - Default
    * - ``clock``
-     - Clock signal that defines the domain
+     - Clock signal that defines the domain.
      - 
    * - ``reset``
-     - Reset signal. If a register exists which needs a reset and the clock domain doesn't provide one, an error message will be displayed
+     - Reset signal. If a register exists which needs a reset and the clock domain doesn't provide one,
+       an error message will be displayed.
      - null
    * - ``softReset``
-     - Reset which infers an additional synchronous reset
+     - Reset which infers an additional synchronous reset.
      - null
    * - ``clockEnable``
-     - The goal of this signal is to disable the clock on the whole clock domain without having to manually implement that on each synchronous element
+     - The goal of this signal is to disable the clock on the whole clock domain without having to manually 
+       implement that on each synchronous element
      - null
    * - ``frequency``
      - Allows you to specify the frequency of the given clock domain and later read it in your design.
-       This parameter does not generate and PLL or other hardware to control the frequency
+       This parameter does not generate a PLL or more hardware to control the frequency.
      - UnknownFrequency
    * - ``config``
-     - Specify the polarity of signals and the nature of the reset
+     - Specify the polarity of signals and the nature of the reset.
      - Current config
 
 
@@ -516,8 +518,8 @@ A ``SlowArea`` is used to create a new clock domain area which is slower than th
 BootReset
 ^^^^^^^^^
 
-`clockDomain.withBootReset()` could specify register's resetKind as BOOT.
-`clockDomain.withSyncReset()` could specify register's resetKind as SYNC (sync-reset).
+``clockDomain.withBootReset()`` could specify register's resetKind as ``BOOT``.
+``clockDomain.withSyncReset()`` could specify register's resetKind as ``SYNC`` (sync-reset).
 
 .. code-block:: scala