fix some CI issues

Author: piotrfila

core/src/mmio.zig

@@ -135,7 +135,7 @@ pub fn Mmio(comptime PackedT: type, access_type: MmioAccess(PackedT)) type {
         /// A one-field version of modify(), more helpful if `field_name` is comptime calculated.
         pub inline fn modify_one(
             self: *volatile @This(),
-            comptime field_name: []const u8,
+            comptime field_name: [:0]const u8,
             value: @FieldType(underlying_type, field_name),
         ) void {
             // Replace with @Struct when migrating to zig 0.16
@@ -154,6 +154,7 @@ pub fn Mmio(comptime PackedT: type, access_type: MmioAccess(PackedT)) type {
         /// Set field `Field` of this register to `value`.
         /// This is implemented using read-modify-write.
         pub inline fn modify(self: *volatile @This(), fields: anytype) void {
+            @setEvalBranchQuota(10_000);
             check_type_has_all_fields(PackedT, fields);
             const Fields = @TypeOf(fields);
 
@@ -186,6 +187,7 @@ pub fn Mmio(comptime PackedT: type, access_type: MmioAccess(PackedT)) type {
         }
 
         pub inline fn set_mask(self: *volatile @This(), fields: anytype) void {
+            @setEvalBranchQuota(10_000);
             check_type_has_all_fields(PackedT, fields);
             const Fields = @TypeOf(fields);
 
@@ -208,6 +210,7 @@ pub fn Mmio(comptime PackedT: type, access_type: MmioAccess(PackedT)) type {
         }
 
         pub inline fn clear_mask(self: *volatile @This(), fields: anytype) void {
+            @setEvalBranchQuota(10_000);
             check_type_has_all_fields(PackedT, fields);
             const Fields = @TypeOf(fields);
 

port/nordic/nrf5x/src/hal/clocks.zig

@@ -72,7 +72,7 @@ pub const lfclk = struct {
                 while (CLOCK.EVENTS_DONE == 0) {}
             },
             .nrf52 => {
-                CLOCK.TASKS_CAL.raw(1);
+                CLOCK.TASKS_CAL.raw = 1;
                 while (CLOCK.EVENTS_DONE.raw == 0) {}
             },
         }

port/wch/ch32v/src/cpus/qingkev2-rv32ec.zig

@@ -69,7 +69,6 @@ pub inline fn system_init(comptime chip: anytype) void {
     // RCC->CFGR0 &= (uint32_t)0xF8FF0000;
     RCC.CFGR0.modify(.{
         .SW = 0,
-        .SWS = 0,
         .HPRE = 0,
         .ADCPRE = 0,
         .MCO = 0,

port/wch/ch32v/src/cpus/qingkev3-rv32imac.zig

@@ -102,7 +102,6 @@ pub inline fn system_init(comptime chip: anytype) void {
     // RCC->CFGR0 &= (uint32_t)0xF8FF0000;
     RCC.CFGR0.modify(.{
         .SW = 0,
-        .SWS = 0,
         .HPRE = 0,
         .ADCPRE = 0,
         .MCO = 0,

tools/regz/src/gen.zig

@@ -1365,7 +1365,7 @@ fn write_fields_and_access(
                 .read_only => "read_only",
                 .write_only, .write_once => "write_only",
             };
-            try writer.print(".{s} = .{s},\n", .{ data.name, access_str });
+            try writer.print(".{f} = .{s},\n", .{ std.zig.fmtId(data.name), access_str });
         },
         .reserved => |num| try writer.print(".reserved{} = .reserved,\n", .{num}),
         .padding => try writer.writeAll(".padding = .reserved,\n"),