FR: Extract design hierarchy by following synthesis messages

[Paebbels]

Vivado reports when it enters and leaves components for synthesis. This allows for a recreation of the design hierarchy and to assoziate Vivado messages (INFO, WARNING, ...) to certain components.

Synthesis log example:

INFO: [Synth 8-638] synthesizing module 'sync_Bits_Xilinx' [C:/Git/PLC2/Training/StopWatch/src/sync_Bits_Xilinx.vhdl:101]
INFO: [Synth 8-638] synthesizing module 'sync_Bit_Xilinx' [C:/Git/PLC2/Training/StopWatch/src/sync_Bits_Xilinx.vhdl:119]
	Parameter INIT bound to: 1'b0
	Parameter SYNC_DEPTH bound to: 2 - type: integer
	Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'FF1_METASTABILITY_FFS' to cell 'FD' [C:/Git/PLC2/Training/StopWatch/src/sync_Bits_Xilinx.vhdl:144]
	Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'FF2' to cell 'FD' [C:/Git/PLC2/Training/StopWatch/src/sync_Bits_Xilinx.vhdl:154]
INFO: [Synth 8-256] done synthesizing module 'sync_Bit_Xilinx' (0#1) [C:/Git/PLC2/Training/StopWatch/src/sync_Bits_Xilinx.vhdl:119]
INFO: [Synth 8-256] done synthesizing module 'sync_Bits_Xilinx' (0#1) [C:/Git/PLC2/Training/StopWatch/src/sync_Bits_Xilinx.vhdl:101]

Recreated hierarchy example:

o- sync_Bits_Xilinx
   |
   o- sync_Bit_Xilinx
      |
      o- FD
      o- FD