Create not.v

Author: galihru

examples/verilog/not.v

@@ -0,0 +1,13 @@
+module visual_circuit(
+    input wire input1,
+    output wire output1
+);
+
+    // Internal wires
+    wire not_out1;
+
+    // Logic implementation
+    assign not_out1 = ~input1;
+    assign output1 = not_out1;
+
+endmodule