Skip to content

Actions: intel/isa-l

Actions

All workflows

Actions

Loading...
Loading

Showing runs from all workflows
222 workflow runs
222 workflow runs

Filter by Event

Filter by Status

Filter by Branch

Filter by Actor

raid: keep sub and jcc in sequence to enable macrofusion. Continous integration #393: Commit c0a10ca pushed by pablodelara
28m 36s master
master
28m 36s
erasure_code: add prefetch and vsetvli optimization Continous integration #392: Pull request #351 synchronize by lvshuo2016
1h 26m 43s lvshuo2016:riscv-optimize
lvshuo2016:riscv-optimize
1h 26m 43s
erasure_code: add prefetch and vsetvli optimization Continous integration #391: Pull request #351 synchronize by lvshuo2016
52m 14s lvshuo2016:riscv-optimize
lvshuo2016:riscv-optimize
52m 14s
erasure_code: xgft loading optimization for AVX2 & dispatch opimization Continous integration #389: Pull request #365 opened by MaodiMa
40m 53s MaodiMa:master
MaodiMa:master
40m 53s
crc: Add vector-accelerated assembly code for RISC-V 64-bit architecture with Zvbc instruction set Continous integration #388: Pull request #350 synchronize by yinlenree
53m 32s zte-riscv:add-crc-riscv-vector-support
zte-riscv:add-crc-riscv-vector-support
53m 32s
Keep sub and jcc in sequence to enable macrofusion. Continous integration #385: Pull request #363 synchronize by Shark64
50s Shark64:macrofusion-2
Shark64:macrofusion-2
50s
erasure_code: add prefetch and vsetvli optimization Continous integration #384: Pull request #351 synchronize by lvshuo2016
35m 0s lvshuo2016:riscv-optimize
lvshuo2016:riscv-optimize
35m 0s
shim: update README (#111) Continous integration #381: Commit 09d7b05 pushed by pablodelara
29m 11s master
master
29m 11s
erasure_code: add prefetch and vsetvli optimization Continous integration #380: Pull request #351 synchronize by lvshuo2016
54m 35s lvshuo2016:riscv-optimize
lvshuo2016:riscv-optimize
54m 35s
aarch64: Use NEON when SVE width is 128 bits Continous integration #379: Commit aedcd37 pushed by pablodelara
48m 3s master
master
48m 3s
Keep sub and jcc in sequence to enable macrofusion. Continous integration #378: Pull request #363 opened by Shark64
47m 35s Shark64:macrofusion-2
Shark64:macrofusion-2
47m 35s
crc: Add vector-accelerated assembly code for RISC-V 64-bit architecture with Zvbc instruction set Continous integration #377: Pull request #350 synchronize by yinlenree
43m 6s zte-riscv:add-crc-riscv-vector-support
zte-riscv:add-crc-riscv-vector-support
43m 6s
crc: Add vector-accelerated assembly code for RISC-V 64-bit architecture with Zvbc instruction set Continous integration #376: Pull request #350 synchronize by yinlenree
42m 20s zte-riscv:add-crc-riscv-vector-support
zte-riscv:add-crc-riscv-vector-support
42m 20s
crc: Add vector-accelerated assembly code for RISC-V 64-bit architecture with Zvbc instruction set Continous integration #375: Pull request #350 synchronize by yinlenree
56m 20s zte-riscv:add-crc-riscv-vector-support
zte-riscv:add-crc-riscv-vector-support
56m 20s
erasure_code: add prefetch and vsetvli optimization Continous integration #374: Pull request #351 synchronize by lvshuo2016
47m 42s lvshuo2016:riscv-optimize
lvshuo2016:riscv-optimize
47m 42s
erasure_code: add prefetch and vsetvli optimization Continous integration #373: Pull request #351 synchronize by lvshuo2016
13m 4s lvshuo2016:riscv-optimize
lvshuo2016:riscv-optimize
13m 4s
crc: Add vector-accelerated assembly code for RISC-V 64-bit architecture with Zvbc instruction set Continous integration #371: Pull request #350 synchronize by yinlenree
1h 24m 7s zte-riscv:add-crc-riscv-vector-support
zte-riscv:add-crc-riscv-vector-support
1h 24m 7s
crc: only prefetch data that will be consumed for VPCLMUL functions Continous integration #369: Commit e677f66 pushed by pablodelara
40m 6s master
master
40m 6s
erasure_code: add prefetch and vsetvli optimization Continous integration #368: Pull request #351 synchronize by lvshuo2016
45m 54s lvshuo2016:riscv-optimize
lvshuo2016:riscv-optimize
45m 54s
Optimize instruction scheduling in gf_*vect_dot_prod_neon Continous integration #363: Pull request #349 synchronize by AWSjswinney
47m 22s AWSjswinney:jswinney/2025-07-21-scheduling-cleanup
AWSjswinney:jswinney/2025-07-21-scheduling-cleanup
47m 22s
igzip: Fix aarch64 registry width for bfinal Continous integration #360: Commit a46e3f1 pushed by pablodelara
42m 30s master
master
42m 30s
erasure_code: add prefetch and vsetvli optimization Continous integration #359: Pull request #351 synchronize by lvshuo2016
1h 7m 7s lvshuo2016:riscv-optimize
lvshuo2016:riscv-optimize
1h 7m 7s
erasure_code: add prefetch and vsetvli optimization Continous integration #357: Pull request #351 synchronize by lvshuo2016
52m 58s lvshuo2016:riscv-optimize
lvshuo2016:riscv-optimize
52m 58s
crc: Add vector-accelerated assembly code for RISC-V 64-bit architecture with Zvbc instruction set Continous integration #354: Pull request #350 synchronize by yinlenree
1h 3m 23s zte-riscv:add-crc-riscv-vector-support
zte-riscv:add-crc-riscv-vector-support
1h 3m 23s
Small micro-optimizations for raid algos. Continous integration #352: Pull request #359 opened by Shark64
52m 50s Shark64:macrofusion
Shark64:macrofusion
52m 50s