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tenyr aspires to be a complete 32-bit computing environment (simulated architecture, operating system, compiler, utilities). It is very much a work in progress. Preliminary binutils including a assembler / disassembler (tas) and simulator (tsim) exist, as well as an HDL implementation in Verilog and a nascent Forth implementation.

Binaries for some architectures are generated for many tagged revisions and can be downloaded here or from the downloads tab on tenyr's github page.

The tenyr architecture has the following properties :

• single-core (no SMP, no NUMA, no threads, no multicore)
• pure 32-bit
  • word-addressed (no endianness)
  • no concept of any data size larger or smaller than 32 bits (no bytes)
  • fixed-width, 32-bit instructions
• 16 integer registers named A - P
  • register A is always zero
  • registers B through O are general-purpose
  • register P is IP (instruction pointer)
    • can be read and written directly
    • points to next instruction
• two's complement
  • true = -1 = 0xffffffff, false = 0 = 0x00000000
• no hardware stack support
  • the O register is used to maintain a stack, but only by convention, in software
• no hardware floating-point
  • software floating-point support is possible but not planned
• no integer divide (not convenient to synthesis)
• all devices and all I/O are memory-mapped (no special I/O instructions)