c: Add attribute to use reverse XOR

Author: bwrsandman

clang/include/clang/Basic/Attr.td

@@ -4946,3 +4946,10 @@ def MOV32rr_REV: InheritableAttr {
   let Documentation = [Undocumented];
   let SimpleHandler = 1;
 }
+
+def XOR32rr_REV: InheritableAttr {
+  let Spellings = [GNU<"XOR32rr_REV">];
+  let Subjects = SubjectList<[Function]>;
+  let Documentation = [Undocumented];
+  let SimpleHandler = 1;
+}

clang/lib/CodeGen/CGCall.cpp

@@ -2391,6 +2391,8 @@ void CodeGenModule::ConstructAttributeList(StringRef Name,
       FuncAttrs.addAttribute(llvm::Attribute::Convergent);
     if (TargetDecl->hasAttr<MOV32rr_REVAttr>())
       FuncAttrs.addAttribute(llvm::Attribute::MOV32rr_REV);
+    if (TargetDecl->hasAttr<XOR32rr_REVAttr>())
+      FuncAttrs.addAttribute(llvm::Attribute::XOR32rr_REV);
 
     if (const FunctionDecl *Fn = dyn_cast<FunctionDecl>(TargetDecl)) {
       AddAttributesFromFunctionProtoType(

clang/lib/Sema/SemaDeclAttr.cpp

@@ -7355,6 +7355,10 @@ ProcessDeclAttribute(Sema &S, Scope *scope, Decl *D, const ParsedAttr &AL,
   case clang::ParsedAttr::AT_MOV32rr_REV:
     handleSimpleAttribute<MOV32rr_REVAttr>(S, D, AL);
     break;
+
+  case clang::ParsedAttr::AT_XOR32rr_REV:
+    handleSimpleAttribute<XOR32rr_REVAttr>(S, D, AL);
+    break;
   }
 }
 

llvm/include/llvm/Bitcode/LLVMBitCodes.h

@@ -788,6 +788,7 @@ enum AttributeKindCodes {
   ATTR_KIND_NO_EXT = 99,
   ATTR_KIND_NO_DIVERGENCE_SOURCE = 100,
   ATTR_MOV32rr_REV = 101,
+  ATTR_XOR32rr_REV = 102,
 };
 
 enum ComdatSelectionKindCodes {

llvm/include/llvm/IR/Attributes.td

@@ -467,5 +467,6 @@ def : MergeRule<"adjustMinLegalVectorWidth">;
 def : MergeRule<"adjustNullPointerValidAttr">;
 def : MergeRule<"setAND<MustProgressAttr>">;
 
-/// Use alternative MOV instruction opcode.
+/// Use alternative MOV and XOR instruction opcode.
 def MOV32rr_REV : EnumAttr<"MOV32rr_REV", IntersectPreserve, [FnAttr]>;
+def XOR32rr_REV : EnumAttr<"XOR32rr_REV", IntersectPreserve, [FnAttr]>;

llvm/lib/Bitcode/Writer/BitcodeWriter.cpp

@@ -907,6 +907,8 @@ static uint64_t getAttrKindEncoding(Attribute::AttrKind Kind) {
     return bitc::ATTR_KIND_NO_EXT;
   case Attribute::MOV32rr_REV:
     return bitc::ATTR_MOV32rr_REV;
+  case Attribute::XOR32rr_REV:
+    return bitc::ATTR_XOR32rr_REV;
   case Attribute::EndAttrKinds:
     llvm_unreachable("Can not encode end-attribute kinds marker.");
   case Attribute::None:

llvm/lib/Target/X86/X86InstrInfo.cpp

@@ -5973,9 +5973,11 @@ static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII,
   MachineBasicBlock &MBB = *MIB->getParent();
   const DebugLoc &DL = MIB->getDebugLoc();
   Register Reg = MIB.getReg(0);
+  MachineFunction &MF = *MBB.getParent();
+  const Function &F = MF.getFunction();
 
   // Insert the XOR.
-  BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg)
+  BuildMI(MBB, MIB.getInstr(), DL, TII.get((F.hasFnAttribute(Attribute::AttrKind::XOR32rr_REV) ? X86::XOR32rr_REV : X86::XOR32rr)), Reg)
       .addReg(Reg, RegState::Undef)
       .addReg(Reg, RegState::Undef);
 
@@ -6075,10 +6077,11 @@ static void expandLoadStackGuard(MachineInstrBuilder &MIB,
 static bool expandXorFP(MachineInstrBuilder &MIB, const TargetInstrInfo &TII) {
   MachineBasicBlock &MBB = *MIB->getParent();
   MachineFunction &MF = *MBB.getParent();
+  const Function &F = MF.getFunction();
   const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
   const X86RegisterInfo *TRI = Subtarget.getRegisterInfo();
   unsigned XorOp =
-      MIB->getOpcode() == X86::XOR64_FP ? X86::XOR64rr : X86::XOR32rr;
+      MIB->getOpcode() == X86::XOR64_FP ? X86::XOR64rr : (F.hasFnAttribute(Attribute::AttrKind::XOR32rr_REV) ? X86::XOR32rr_REV : X86::XOR32rr);
   MIB->setDesc(TII.get(XorOp));
   MIB.addReg(TRI->getFrameRegister(MF), RegState::Undef);
   return true;
@@ -6144,10 +6147,14 @@ static bool expandSHXDROT(MachineInstrBuilder &MIB, const MCInstrDesc &Desc) {
 
 bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
   bool HasAVX = Subtarget.hasAVX();
-  MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
+
+  MachineBasicBlock &MBB = *MI.getParent();
+  MachineFunction &MF = *MBB.getParent();
+  MachineInstrBuilder MIB(MF, MI);
+  const Function &F = MF.getFunction();
   switch (MI.getOpcode()) {
   case X86::MOV32r0:
-    return Expand2AddrUndef(MIB, get(X86::XOR32rr));
+    return Expand2AddrUndef(MIB, get(F.hasFnAttribute(Attribute::AttrKind::XOR32rr_REV) ? X86::XOR32rr_REV : X86::XOR32rr));
   case X86::MOV32r1:
     return expandMOV32r1(MIB, *this, /*MinusOne=*/false);
   case X86::MOV32r_1:

llvm/lib/Transforms/Utils/CodeExtractor.cpp

@@ -951,6 +951,7 @@ Function *CodeExtractor::constructFunctionDeclaration(
       case Attribute::NoProfile:
       case Attribute::SkipProfile:
       case Attribute::MOV32rr_REV:
+      case Attribute::XOR32rr_REV:
         break;
       // These attributes cannot be applied to functions.
       case Attribute::Alignment: