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Add ctrl_reg variant without L0 statistics
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‎.github/workflows/lint.yml‎

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@@ -26,6 +26,8 @@ jobs:
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exclude_paths: |
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./src/ctrl_unit/cluster_icache_ctrl_reg_top.sv
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./src/ctrl_unit/cluster_icache_ctrl_reg_pkg.sv
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./src/ctrl_unit/cluster_icache_ctrl_perfctr_reg_top.sv
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./src/ctrl_unit/cluster_icache_ctrl_perfctr_reg_pkg.sv
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github_token: ${{ secrets.GITHUB_TOKEN }}
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fail_on_error: true
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reviewdog_reporter: github-check

‎Bender.yml‎

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@@ -43,6 +43,10 @@ sources:
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- src/ctrl_unit/cluster_icache_ctrl_reg_pkg.sv
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- src/ctrl_unit/cluster_icache_ctrl_reg_top.sv
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- src/ctrl_unit/cluster_icache_ctrl_unit.sv
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- files: # ctrl_unit
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- src/ctrl_unit/cluster_icache_ctrl_perfctr_reg_pkg.sv
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- src/ctrl_unit/cluster_icache_ctrl_perfctr_reg_top.sv
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- src/ctrl_unit/cluster_icache_ctrl_perfctr_unit.sv
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- target: test
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files:
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- test/snitch_icache_l0_tb.sv

‎Makefile‎

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@@ -11,6 +11,7 @@ VLOG_FLAGS += +cover=sbecft
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CTRL_UNIT_DIR = src/ctrl_unit
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CTRL_UNIT = $(CTRL_UNIT_DIR)/cluster_icache_ctrl
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CTRL_UNIT_PERF = $(CTRL_UNIT_DIR)/cluster_icache_ctrl_perfctr
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Bender.lock:
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$(BENDER) update
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$(BENDER) checkout
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.PHONY: gen_hw
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gen_hw: .bender $(CTRL_UNIT)_reg_top.sv
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gen_hw: .bender $(CTRL_UNIT)_reg_top.sv $(CTRL_UNIT_PERF)_reg_top.sv
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$(CTRL_UNIT)_reg_top.sv: .bender $(CTRL_UNIT).hjson
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python $(shell $(BENDER) path register_interface)/vendor/lowrisc_opentitan/util/regtool.py $(CTRL_UNIT).hjson -t $(CTRL_UNIT_DIR) -r
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$(CTRL_UNIT_PERF)_reg_top.sv: .bender $(CTRL_UNIT_PERF).hjson
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python $(shell $(BENDER) path register_interface)/vendor/lowrisc_opentitan/util/regtool.py $(CTRL_UNIT_PERF).hjson -t $(CTRL_UNIT_DIR) -r
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compile.tcl: .bender Bender.yml Bender.lock
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$(BENDER) script vsim -t test \
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--vlog-arg="$(VLOG_FLAGS)" \

‎src/ctrl_unit/cluster_icache_ctrl_perfctr.hjson‎

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// Copyright 2024 ETH Zurich and University of Bologna.
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// Solderpad Hardware License, Version 0.51, see LICENSE for details.
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// SPDX-License-Identifier: SHL-0.51
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{
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name: "cluster_icache_ctrl_perfctr",
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clock_primary: "clk_i",
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reset_primary: "rst_ni",
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bus_interfaces: [
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{ protocol: "reg_iface",
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direction: "device"
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}
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],
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param_list: [
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{ name: "NumCores",
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desc: "Number of cores",
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default: "8"
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},
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{ name: "NumL0Events",
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desc: "Number of L0 events",
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default: "5" // Use performance counters for L0 events
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},
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{ name: "NumL1Events",
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desc: "Number of L1 events",
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default: "4"
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},
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{ name: "NumAvailableCounters",
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desc: "Number of available counters",
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default: "4" // NumL1Events
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},
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],
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regwidth: "32",
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registers: [
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{ name: "enable",
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desc: "",
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swaccess: "rw",
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hwaccess: "hro",
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fields: [
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{ bits: "0",
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name: "enable",
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desc: "",
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resval: 0x1
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}
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]
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},
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{ name: "flush",
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desc: "Flush all levels of the cache",
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swaccess: "rw",
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hwaccess: "hrw",
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hwqe: "true",
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hwext: "true",
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fields: [
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{ bits: "0",
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name: "flush",
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desc: "",
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resval: 0x0
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}
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]
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},
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{ name: "flush_l1_only",
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desc: "not yet functional",
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swaccess: "rw",
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hwaccess: "hrw",
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hwext: "true",
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hwqe: "true",
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fields: [
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{ bits: "0",
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name: "flush",
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desc: "",
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resval: 0x0
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}
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]
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},
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{ name: "sel_flush_icache",
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desc: "flush specified L0 banks (and currently the complete L1)",
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swaccess: "rw",
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hwaccess: "hrw",
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hwext: "true",
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hwqe: "true",
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fields: [
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{ bits: "NumCores-1:0",
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name: "flush",
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desc: "",
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resval: 0x0000_0000
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}
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]
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},
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{ name: "clear_counters",
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desc: "Clear all performance counters",
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swaccess: "rw",
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hwaccess: "hrw",
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hwqe: "true",
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hwext: "true",
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fields: [
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{ bits: "0",
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name: "clear",
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desc: "",
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resval: 0x0
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}
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]
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},
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{ name: "enable_counters",
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desc: "Enable performance counters",
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swaccess: "rw",
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hwaccess: "hro",
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fields: [
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{ bits: "0",
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name: "enable",
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desc: "",
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resval: 0x1
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}
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]
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},
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{ skipto: "0x1C" },
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{ name: "enable_prefetch",
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desc: "Enable prefetching",
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swaccess: "rw",
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hwaccess: "hro",
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fields: [
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{ bits: "0",
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name: "enable",
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desc: "",
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resval: 0x1
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}
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]
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},
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{ multireg: {
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name: "counters",
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desc: "Performance counters",
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count: "NumAvailableCounters",
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cname: "id",
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swaccess: "rw0c",
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hwaccess: "hrw",
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fields: [
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{ bits: "31:0",
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name: "counter",
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desc: "",
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resval: 0x0000_0000
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}
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]
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}
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},
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],
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}

‎src/ctrl_unit/cluster_icache_ctrl_perfctr_reg_pkg.sv‎

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// Copyright lowRISC contributors.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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//
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// Register Package auto-generated by `reggen` containing data structure
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package cluster_icache_ctrl_perfctr_reg_pkg;
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// Param list
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parameter int NumCores = 8;
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parameter int NumL0Events = 5;
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parameter int NumL1Events = 4;
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parameter int NumAvailableCounters = 4;
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// Address widths within the block
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parameter int BlockAw = 6;
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////////////////////////////
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// Typedefs for registers //
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////////////////////////////
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typedef struct packed {
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logic q;
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} cluster_icache_ctrl_perfctr_reg2hw_enable_reg_t;
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typedef struct packed {
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logic q;
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logic qe;
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} cluster_icache_ctrl_perfctr_reg2hw_flush_reg_t;
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typedef struct packed {
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logic q;
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logic qe;
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} cluster_icache_ctrl_perfctr_reg2hw_flush_l1_only_reg_t;
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typedef struct packed {
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logic [7:0] q;
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logic qe;
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} cluster_icache_ctrl_perfctr_reg2hw_sel_flush_icache_reg_t;
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typedef struct packed {
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logic q;
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logic qe;
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} cluster_icache_ctrl_perfctr_reg2hw_clear_counters_reg_t;
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typedef struct packed {
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logic q;
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} cluster_icache_ctrl_perfctr_reg2hw_enable_counters_reg_t;
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typedef struct packed {
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logic q;
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} cluster_icache_ctrl_perfctr_reg2hw_enable_prefetch_reg_t;
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typedef struct packed {
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logic [31:0] q;
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} cluster_icache_ctrl_perfctr_reg2hw_counters_mreg_t;
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typedef struct packed {
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logic d;
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} cluster_icache_ctrl_perfctr_hw2reg_flush_reg_t;
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typedef struct packed {
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logic d;
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} cluster_icache_ctrl_perfctr_hw2reg_flush_l1_only_reg_t;
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typedef struct packed {
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logic [7:0] d;
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} cluster_icache_ctrl_perfctr_hw2reg_sel_flush_icache_reg_t;
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typedef struct packed {
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logic d;
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} cluster_icache_ctrl_perfctr_hw2reg_clear_counters_reg_t;
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typedef struct packed {
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logic [31:0] d;
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logic de;
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} cluster_icache_ctrl_perfctr_hw2reg_counters_mreg_t;
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// Register -> HW type
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typedef struct packed {
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cluster_icache_ctrl_perfctr_reg2hw_enable_reg_t enable; // [145:145]
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cluster_icache_ctrl_perfctr_reg2hw_flush_reg_t flush; // [144:143]
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cluster_icache_ctrl_perfctr_reg2hw_flush_l1_only_reg_t flush_l1_only; // [142:141]
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cluster_icache_ctrl_perfctr_reg2hw_sel_flush_icache_reg_t sel_flush_icache; // [140:132]
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cluster_icache_ctrl_perfctr_reg2hw_clear_counters_reg_t clear_counters; // [131:130]
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cluster_icache_ctrl_perfctr_reg2hw_enable_counters_reg_t enable_counters; // [129:129]
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cluster_icache_ctrl_perfctr_reg2hw_enable_prefetch_reg_t enable_prefetch; // [128:128]
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cluster_icache_ctrl_perfctr_reg2hw_counters_mreg_t [3:0] counters; // [127:0]
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} cluster_icache_ctrl_perfctr_reg2hw_t;
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// HW -> register type
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typedef struct packed {
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cluster_icache_ctrl_perfctr_hw2reg_flush_reg_t flush; // [142:142]
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cluster_icache_ctrl_perfctr_hw2reg_flush_l1_only_reg_t flush_l1_only; // [141:141]
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cluster_icache_ctrl_perfctr_hw2reg_sel_flush_icache_reg_t sel_flush_icache; // [140:133]
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cluster_icache_ctrl_perfctr_hw2reg_clear_counters_reg_t clear_counters; // [132:132]
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cluster_icache_ctrl_perfctr_hw2reg_counters_mreg_t [3:0] counters; // [131:0]
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} cluster_icache_ctrl_perfctr_hw2reg_t;
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// Register offsets
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parameter logic [BlockAw-1:0] CLUSTER_ICACHE_CTRL_PERFCTR_ENABLE_OFFSET = 6'h 0;
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parameter logic [BlockAw-1:0] CLUSTER_ICACHE_CTRL_PERFCTR_FLUSH_OFFSET = 6'h 4;
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parameter logic [BlockAw-1:0] CLUSTER_ICACHE_CTRL_PERFCTR_FLUSH_L1_ONLY_OFFSET = 6'h 8;
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parameter logic [BlockAw-1:0] CLUSTER_ICACHE_CTRL_PERFCTR_SEL_FLUSH_ICACHE_OFFSET = 6'h c;
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parameter logic [BlockAw-1:0] CLUSTER_ICACHE_CTRL_PERFCTR_CLEAR_COUNTERS_OFFSET = 6'h 10;
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parameter logic [BlockAw-1:0] CLUSTER_ICACHE_CTRL_PERFCTR_ENABLE_COUNTERS_OFFSET = 6'h 14;
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parameter logic [BlockAw-1:0] CLUSTER_ICACHE_CTRL_PERFCTR_ENABLE_PREFETCH_OFFSET = 6'h 1c;
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parameter logic [BlockAw-1:0] CLUSTER_ICACHE_CTRL_PERFCTR_COUNTERS_0_OFFSET = 6'h 20;
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parameter logic [BlockAw-1:0] CLUSTER_ICACHE_CTRL_PERFCTR_COUNTERS_1_OFFSET = 6'h 24;
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parameter logic [BlockAw-1:0] CLUSTER_ICACHE_CTRL_PERFCTR_COUNTERS_2_OFFSET = 6'h 28;
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parameter logic [BlockAw-1:0] CLUSTER_ICACHE_CTRL_PERFCTR_COUNTERS_3_OFFSET = 6'h 2c;
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// Reset values for hwext registers and their fields
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parameter logic [0:0] CLUSTER_ICACHE_CTRL_PERFCTR_FLUSH_RESVAL = 1'h 0;
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parameter logic [0:0] CLUSTER_ICACHE_CTRL_PERFCTR_FLUSH_FLUSH_RESVAL = 1'h 0;
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parameter logic [0:0] CLUSTER_ICACHE_CTRL_PERFCTR_FLUSH_L1_ONLY_RESVAL = 1'h 0;
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parameter logic [0:0] CLUSTER_ICACHE_CTRL_PERFCTR_FLUSH_L1_ONLY_FLUSH_RESVAL = 1'h 0;
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parameter logic [7:0] CLUSTER_ICACHE_CTRL_PERFCTR_SEL_FLUSH_ICACHE_RESVAL = 8'h 0;
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parameter logic [7:0] CLUSTER_ICACHE_CTRL_PERFCTR_SEL_FLUSH_ICACHE_FLUSH_RESVAL = 8'h 0;
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parameter logic [0:0] CLUSTER_ICACHE_CTRL_PERFCTR_CLEAR_COUNTERS_RESVAL = 1'h 0;
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parameter logic [0:0] CLUSTER_ICACHE_CTRL_PERFCTR_CLEAR_COUNTERS_CLEAR_RESVAL = 1'h 0;
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// Register index
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typedef enum int {
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CLUSTER_ICACHE_CTRL_PERFCTR_ENABLE,
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CLUSTER_ICACHE_CTRL_PERFCTR_FLUSH,
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CLUSTER_ICACHE_CTRL_PERFCTR_FLUSH_L1_ONLY,
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CLUSTER_ICACHE_CTRL_PERFCTR_SEL_FLUSH_ICACHE,
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CLUSTER_ICACHE_CTRL_PERFCTR_CLEAR_COUNTERS,
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CLUSTER_ICACHE_CTRL_PERFCTR_ENABLE_COUNTERS,
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CLUSTER_ICACHE_CTRL_PERFCTR_ENABLE_PREFETCH,
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CLUSTER_ICACHE_CTRL_PERFCTR_COUNTERS_0,
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CLUSTER_ICACHE_CTRL_PERFCTR_COUNTERS_1,
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CLUSTER_ICACHE_CTRL_PERFCTR_COUNTERS_2,
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CLUSTER_ICACHE_CTRL_PERFCTR_COUNTERS_3
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} cluster_icache_ctrl_perfctr_id_e;
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// Register width information to check illegal writes
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parameter logic [3:0] CLUSTER_ICACHE_CTRL_PERFCTR_PERMIT [11] = '{
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4'b 0001, // index[ 0] CLUSTER_ICACHE_CTRL_PERFCTR_ENABLE
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4'b 0001, // index[ 1] CLUSTER_ICACHE_CTRL_PERFCTR_FLUSH
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4'b 0001, // index[ 2] CLUSTER_ICACHE_CTRL_PERFCTR_FLUSH_L1_ONLY
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4'b 0001, // index[ 3] CLUSTER_ICACHE_CTRL_PERFCTR_SEL_FLUSH_ICACHE
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4'b 0001, // index[ 4] CLUSTER_ICACHE_CTRL_PERFCTR_CLEAR_COUNTERS
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4'b 0001, // index[ 5] CLUSTER_ICACHE_CTRL_PERFCTR_ENABLE_COUNTERS
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4'b 0001, // index[ 6] CLUSTER_ICACHE_CTRL_PERFCTR_ENABLE_PREFETCH
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4'b 1111, // index[ 7] CLUSTER_ICACHE_CTRL_PERFCTR_COUNTERS_0
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4'b 1111, // index[ 8] CLUSTER_ICACHE_CTRL_PERFCTR_COUNTERS_1
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4'b 1111, // index[ 9] CLUSTER_ICACHE_CTRL_PERFCTR_COUNTERS_2
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4'b 1111 // index[10] CLUSTER_ICACHE_CTRL_PERFCTR_COUNTERS_3
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};
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endpackage
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