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lines changed Original file line number Diff line number Diff line change 11.bender
2- Bender.lock
32compile.tcl
43
54modelsim.ini
Original file line number Diff line number Diff line change 44
55variables :
66 GIT_STRATEGY : clone
7- VSIM : questa-2023.4 vsim
7+ VSIM : questa-2025.1 vsim
88
99test_l0 :
1010 script :
Original file line number Diff line number Diff line change 1+ packages:
2+ axi:
3+ revision: f07498d53ecd5518b277c7d213ec3b71ca4df93c
4+ version: 0.39.7
5+ source:
6+ Git: https://github.com/pulp-platform/axi.git
7+ dependencies:
8+ - common_cells
9+ - common_verification
10+ - tech_cells_generic
11+ common_cells:
12+ revision: 9afda9abb565971649c2aa0985639c096f351171
13+ version: 1.38.0
14+ source:
15+ Git: https://github.com/pulp-platform/common_cells.git
16+ dependencies:
17+ - common_verification
18+ - tech_cells_generic
19+ common_verification:
20+ revision: fb1885f48ea46164a10568aeff51884389f67ae3
21+ version: 0.2.5
22+ source:
23+ Git: https://github.com/pulp-platform/common_verification.git
24+ dependencies: []
25+ scm:
26+ revision: 472f99affe44ff7b282b519c047a3cfeb35b16c6
27+ version: 1.2.0
28+ source:
29+ Git: https://github.com/pulp-platform/scm.git
30+ dependencies:
31+ - tech_cells_generic
32+ tech_cells_generic:
33+ revision: a9cae21902e75b1434328ecf36f85327ba5717de
34+ version: 0.2.11
35+ source:
36+ Git: https://github.com/pulp-platform/tech_cells_generic.git
37+ dependencies:
38+ - common_verification
Original file line number Diff line number Diff line change @@ -6,6 +6,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
66
77
88## Unreleased
9+ ### Changed
10+ - Rename signals indicating cache way from ` *set* ` to ` *way* ` .
11+
12+ ## 0.2.0 - 24.02.2025
913### Fixed
1014- lookup_serial: Make ` write_ready_o ` independent of ` write_valid_i ` .
1115- Fix L0 testbench.
Original file line number Diff line number Diff line change @@ -74,23 +74,23 @@ class semirand_axi_master #(
7474
7575 task send_ars (input int n_reads);
7676 automatic logic rand_success;
77- automatic ax_beat_t ar_beat = new_rand_burst (1'b1 );
77+ automatic ax_beat_t ar_beat = new_rand_burst (1'b1 , '0 );
7878 repeat (n_reads) begin
7979 automatic id_t id;
8080 automatic logic jump;
8181 // Increment address per default, randomize sporadically
8282 rand_success = std:: randomize (jump) with { jump dist { 1'b0 : = 90 , 1'b1 : = 10 } ;} ;
8383 assert (rand_success);
8484 if (jump) begin
85- ar_beat = new_rand_burst (1'b1 );
85+ ar_beat = new_rand_burst (1'b1 , '0 );
8686 end else begin
8787 ar_beat.ax_addr = ar_beat.ax_addr + AXI_ADDR_INCR ;
8888 end
8989 while (tot_r_flight_cnt >= MAX_READ_TXNS ) begin
9090 rand_wait (1 , 1 );
9191 end
9292 if (AXI_EXCLS ) begin
93- rand_excl_ar (ar_beat);
93+ rand_excl_ar (ar_beat, '0 );
9494 end
9595 if (AXI_ATOPS ) begin
9696 // The ID must not be the same as that of any in-flight ATOP.
@@ -129,7 +129,7 @@ class semirand_axi_master #(
129129 end
130130 recv_rs (ar_done, aw_done);
131131 begin
132- create_aws (n_writes);
132+ create_aws (n_writes, '0 );
133133 aw_done = 1'b1 ;
134134 end
135135 send_aws (aw_done);
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