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Fix CI, bump deps, update changelog, ensure locked deps for CI
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+47
-6
lines changed

5 files changed

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.gitignore

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.bender
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Bender.lock
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compile.tcl
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modelsim.ini

.gitlab-ci.yml

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variables:
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GIT_STRATEGY: clone
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VSIM: questa-2023.4 vsim
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VSIM: questa-2025.1 vsim
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test_l0:
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script:

Bender.lock

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packages:
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axi:
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revision: f07498d53ecd5518b277c7d213ec3b71ca4df93c
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version: 0.39.7
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source:
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Git: https://github.com/pulp-platform/axi.git
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dependencies:
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- common_cells
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- common_verification
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- tech_cells_generic
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common_cells:
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revision: 9afda9abb565971649c2aa0985639c096f351171
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version: 1.38.0
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source:
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Git: https://github.com/pulp-platform/common_cells.git
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dependencies:
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- common_verification
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- tech_cells_generic
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common_verification:
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revision: fb1885f48ea46164a10568aeff51884389f67ae3
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version: 0.2.5
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source:
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Git: https://github.com/pulp-platform/common_verification.git
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dependencies: []
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scm:
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revision: 472f99affe44ff7b282b519c047a3cfeb35b16c6
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version: 1.2.0
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source:
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Git: https://github.com/pulp-platform/scm.git
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dependencies:
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- tech_cells_generic
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tech_cells_generic:
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revision: a9cae21902e75b1434328ecf36f85327ba5717de
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version: 0.2.11
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source:
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Git: https://github.com/pulp-platform/tech_cells_generic.git
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dependencies:
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- common_verification

Changelog.md

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@@ -6,6 +6,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
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## Unreleased
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### Changed
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- Rename signals indicating cache way from `*set*` to `*way*`.
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## 0.2.0 - 24.02.2025
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### Fixed
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- lookup_serial: Make `write_ready_o` independent of `write_valid_i`.
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- Fix L0 testbench.

test/snitch_read_only_cache_tb.sv

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@@ -74,23 +74,23 @@ class semirand_axi_master #(
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task send_ars(input int n_reads);
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automatic logic rand_success;
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automatic ax_beat_t ar_beat = new_rand_burst(1'b1);
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automatic ax_beat_t ar_beat = new_rand_burst(1'b1, '0);
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repeat (n_reads) begin
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automatic id_t id;
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automatic logic jump;
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// Increment address per default, randomize sporadically
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rand_success = std::randomize(jump) with {jump dist {1'b0 := 90, 1'b1 := 10};};
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assert(rand_success);
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if (jump) begin
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ar_beat = new_rand_burst(1'b1);
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ar_beat = new_rand_burst(1'b1, '0);
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end else begin
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ar_beat.ax_addr = ar_beat.ax_addr + AXI_ADDR_INCR;
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end
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while (tot_r_flight_cnt >= MAX_READ_TXNS) begin
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rand_wait(1, 1);
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end
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if (AXI_EXCLS) begin
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rand_excl_ar(ar_beat);
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rand_excl_ar(ar_beat, '0);
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end
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if (AXI_ATOPS) begin
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// The ID must not be the same as that of any in-flight ATOP.
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end
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recv_rs(ar_done, aw_done);
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begin
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create_aws(n_writes);
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create_aws(n_writes, '0);
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aw_done = 1'b1;
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end
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send_aws(aw_done);

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