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Create wrapper for PULP cluster
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‎Bender.yml‎

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# Level 3
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- src/snitch_icache.sv
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- src/snitch_read_only_cache.sv
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- target: pulp
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files:
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- src/pulp_icache_wrap.sv
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- target: test
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files:
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- test/snitch_icache_l0_tb.sv

‎src/pulp_icache_wrap.sv‎

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// Copyright 2024 ETH Zurich and University of Bologna.
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// Solderpad Hardware License, Version 0.51, see LICENSE for details.
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// SPDX-License-Identifier: SHL-0.51
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// Michael Rogenmoser <michaero@iis.ee.ethz.ch>
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`include "common_cells/registers.svh"
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/// Porting from hier-icache:
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/// Missing: different line width, banks in L1, L0 is fully associative
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/// [PRI_FETCH_DATA_WIDTH == SH_FETCH_DATA_WIDTH]
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/// [SH_NB_BANKS == 1]
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/// [PRI_NB_WAYS == 1]
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/// [SH_CACHE_LINE == PRI_CACHE_LINE]
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/// NumFetchPorts = NB_CORES
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/// L0_LINE_COUNT = SH_CACHE_SIZE/(bytes per line)
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/// LINE_WIDTH = X_CACHE_LINE * DATA_WIDTH
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/// LINE_COUNT = SH_CACHE_SIZE/(bytes per line)
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/// SET_COUNT = SH_NB_WAYS
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module pulp_icache_wrap #(
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/// Number of request (fetch) ports
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parameter int NumFetchPorts = -1,
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/// L0 Cache Line Count
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parameter int L0_LINE_COUNT = -1,
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/// Cache Line Width
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parameter int LINE_WIDTH = -1,
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/// The number of cache lines per set. Power of two; >= 2.
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parameter int LINE_COUNT = -1,
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/// The set associativity of the cache. Power of two; >= 1.
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parameter int SET_COUNT = 1,
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/// Fetch interface address width. Same as FILL_AW; >= 1.
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parameter int FetchAddrWidth = -1,
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/// Fetch interface data width. Power of two; >= 8.
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parameter int FetchDataWidth = -1,
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/// Fill interface address width. Same as FETCH_AW; >= 1.
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parameter int AxiAddrWidth = -1,
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/// Fill interface data width. Power of two; >= 8.
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parameter int AxiDataWidth = -1,
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/// Configuration input types for memory cuts used in implementation.
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parameter type sram_cfg_data_t = logic,
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parameter type sram_cfg_tag_t = logic,
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parameter type axi_req_t = logic,
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parameter type axi_rsp_t = logic
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) (
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input logic clk_i,
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input logic rst_ni,
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// Processor interface
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input logic [NumFetchPorts-1:0] fetch_req_i,
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input logic [NumFetchPorts-1:0][FetchAddrWidth-1:0] fetch_addr_i,
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output logic [NumFetchPorts-1:0] fetch_gnt_o,
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output logic [NumFetchPorts-1:0] fetch_rvalid_o,
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output logic [NumFetchPorts-1:0][FetchDataWidth-1:0] fetch_rdata_o,
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output logic [NumFetchPorts-1:0] fetch_rerror_o,
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input logic enable_prefetching_i,
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output snitch_icache_pkg::icache_events_t [NumFetchPorts-1:0] icache_events_o,
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input logic [NumFetchPorts-1:0] flush_valid_i,
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output logic [NumFetchPorts-1:0] flush_ready_o,
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// SRAM configs
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input sram_cfg_data_t sram_cfg_data_i,
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input sram_cfg_tag_t sram_cfg_tag_i,
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// AXI interface
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output axi_req_t axi_req_o,
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input axi_rsp_t axi_rsp_i
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);
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localparam int unsigned AdapterType = 1;
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logic [NumFetchPorts-1:0] fetch_valid, fetch_ready, fetch_rerror;
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logic [NumFetchPorts-1:0][FetchAddrWidth-1:0] fetch_addr;
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logic [NumFetchPorts-1:0][FetchDataWidth-1:0] fetch_rdata;
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for (genvar i = 0; i < NumFetchPorts; i++) begin : gen_adapter
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if (AdapterType == 0) begin : gen_response_cut
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// Reuquires the core to keep data applied steady while req is high, may not be guaranteed...
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spill_register #(
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.T (logic [FetchDataWidth-1+1:0]),
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.Bypass(1'b0)
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) i_spill_reg (
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.clk_i,
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.rst_ni,
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.valid_i ( fetch_ready [i] ),
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.ready_o ( /* Unconnected as always ready */ ),
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.data_i ( {fetch_rdata [i], fetch_rerror [i]} ),
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.valid_o ( fetch_rvalid_o[i] ),
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.ready_i ( '1 ),
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.data_o ( {fetch_rdata_o[i], fetch_rerror_o[i]} )
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);
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assign fetch_addr[i] = fetch_addr_i[i];
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assign fetch_valid[i] = fetch_req_i[i];
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assign fetch_gnt_o[i] = fetch_ready[i];
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end else if (AdapterType == 1) begin : gen_request_cut
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logic gnt;
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assign fetch_gnt_o[i] = gnt & fetch_req_i[i];
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spill_register #(
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.T (logic [FetchAddrWidth-1:0]),
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.Bypass(1'b0)
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) i_spill_reg (
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.clk_i,
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.rst_ni,
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.valid_i ( fetch_req_i [i] ),
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.ready_o ( gnt ),
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.data_i ( fetch_addr_i[i] ),
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.valid_o ( fetch_valid [i] ),
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.ready_i ( fetch_ready [i] ),
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.data_o ( fetch_addr [i] )
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);
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assign fetch_rdata_o [i] = fetch_rdata [i];
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assign fetch_rerror_o[i] = fetch_rerror[i];
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assign fetch_rvalid_o[i] = fetch_ready [i] & fetch_valid[i];
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end else begin : gen_flexible_cut
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// This can still be improved, there is still an extra stall cycle sometimes AFAIK...
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logic stalled_d, stalled_q;
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logic spill_valid, spill_ready;
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logic [FetchAddrWidth-1:0] spill_addr;
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spill_register #(
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.T (logic [FetchAddrWidth-1:0]),
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.Bypass(1'b0)
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) i_req_spill_reg (
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.clk_i,
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.rst_ni,
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.valid_i ( fetch_req_i [i] ),
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.ready_o ( fetch_gnt_o [i] ),
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.data_i ( fetch_addr_i[i] ),
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.valid_o ( spill_valid ),
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.ready_i ( spill_ready ),
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.data_o ( spill_addr )
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);
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always_comb begin
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// Keep steady state
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stalled_d = stalled_q;
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// If already stalled
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if (stalled_q) begin
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// only revert back to unstalled state with sufficient gap
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if (!spill_valid && !fetch_req_i[i])
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stalled_d = 1'b0;
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end else begin
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if (fetch_req_i[i] && !fetch_ready[i])
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stalled_d = 1'b1;
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end
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end
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`FF(stalled_q, stalled_d, '0)
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assign fetch_valid[i] = stalled_q ? spill_valid : fetch_req_i[i];
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assign fetch_addr [i] = stalled_q ? spill_addr : fetch_addr_i[i];
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logic spill_rvalid;
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logic spill_rerror;
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logic [FetchDataWidth-1:0] spill_rdata;
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spill_register #(
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.T (logic [FetchDataWidth-1+1:0]),
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.Bypass(1'b0)
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) i_rsp_spill_reg (
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.clk_i,
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.rst_ni,
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.valid_i ( fetch_ready [i] ),
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.ready_o ( /* Unconnected as always ready */ ),
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.data_i ( {fetch_rdata[i], fetch_rerror[i]} ),
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.valid_o ( spill_rvalid ),
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.ready_i ( '1 ),
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.data_o ( {spill_rdata , spill_rerror } )
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);
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assign fetch_rvalid_o[i] = stalled_q ? fetch_ready[i] : spill_rvalid;
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assign fetch_rdata_o [i] = stalled_q ? fetch_rdata [i] : spill_rdata;
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assign fetch_rerror_o[i] = stalled_q ? fetch_rerror[i] : spill_rerror;
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end
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end
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snitch_icache #(
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.NR_FETCH_PORTS ( NumFetchPorts ),
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.L0_LINE_COUNT ( L0_LINE_COUNT ),
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.LINE_WIDTH ( LINE_WIDTH ),
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.LINE_COUNT ( LINE_COUNT ),
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.SET_COUNT ( SET_COUNT ),
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.FETCH_AW ( FetchAddrWidth ),
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.FETCH_DW ( FetchDataWidth ),
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.FILL_AW ( AxiAddrWidth ),
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.FILL_DW ( AxiDataWidth ),
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.L1_TAG_SCM ( 1 ),
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.SERIAL_LOOKUP ( 1 ),
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.NUM_AXI_OUTSTANDING( 4 ),
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.EARLY_LATCH ( 0 ),
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.ISO_CROSSING ( 0 ),
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.sram_cfg_data_t ( sram_cfg_data_t ),
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.sram_cfg_tag_t ( sram_cfg_tag_t ),
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.axi_req_t ( axi_req_t ),
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.axi_rsp_t ( axi_rsp_t )
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) i_snitch_icache (
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.clk_i,
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.clk_d2_i ( clk_i ),
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.rst_ni,
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.enable_prefetching_i,
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.icache_events_o,
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.flush_valid_i,
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.flush_ready_o,
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.inst_addr_i ( fetch_addr ),
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.inst_data_o ( fetch_rdata ),
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.inst_cacheable_i ( {NumFetchPorts{1'b1}} ),
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.inst_valid_i ( fetch_valid ),
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.inst_ready_o ( fetch_ready ),
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.inst_error_o ( fetch_rerror ),
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.sram_cfg_data_i,
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.sram_cfg_tag_i,
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.axi_req_o,
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.axi_rsp_i
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);
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endmodule

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