hw: add support for misaligned vector length in 2x VLSU Spatz

Author: Navaneeth-KunhiPurayil

hw/ip/spatz/src/spatz_doublebw_vlsu.sv

@@ -21,7 +21,8 @@ module spatz_doublebw_vlsu
     parameter  type          spatz_mem_rsp_t    = logic,
     // Dependant parameters. DO NOT CHANGE!
     localparam int  unsigned NrInterfaces       = NrMemPorts / spatz_pkg::N_FU,
-    localparam int  unsigned IdWidth            = idx_width(NrOutstandingLoads)
+    localparam int  unsigned IdWidth            = idx_width(NrOutstandingLoads),
+    localparam int  unsigned SpatzMemBytes      = NrMemPorts * ELENB
   ) (
     input  logic                            clk_i,
     input  logic                            rst_ni,
@@ -482,7 +483,10 @@ module spatz_doublebw_vlsu
         // The second interface starts from half of the vector to straighten the write-back VRF access pattern
         // To ensure that the 2 interfaces do not also conflict at the TCDM, there is HW scrambling of addresses to TCDM
         // such that they access different superbanks.
-        if (!mem_is_indexed && !mem_is_strided && intf == 1) offset += (mem_spatz_req.vl / 2);
+        if (!mem_is_indexed && !mem_is_strided && intf == 1) begin 
+          // Align the vector length with SpatzMemBytes bytes
+          offset += ((mem_spatz_req.vl +  (SpatzMemBytes / 2)) >> $clog2(SpatzMemBytes) << $clog2(SpatzMemBytes)) / 2;
+        end
 
         addr                      = mem_spatz_req.rs1 + offset;
         mem_req_addr[intf][fu]        = (addr >> MAXEW) << MAXEW;
@@ -504,7 +508,7 @@ module spatz_doublebw_vlsu
 
       // The second interface starts from half of the vector to straighten the write-back VRF access pattern
       if (intf == 1) begin
-        vd_vreg_addr[intf] += commit_insn_q.vl / (2 * N_FU * ELENB);
+        vd_vreg_addr[intf] += (commit_insn_q.vl + (SpatzMemBytes / 2)) >> $clog2(SpatzMemBytes);
         vs2_vreg_idx_addr[intf] += ((mem_spatz_req.vl >> (mem_spatz_req.vtype.vsew - int'(mem_spatz_req.op_mem.ew))) / (2 * N_FU * ELENB));
       end
 
@@ -643,6 +647,15 @@ module spatz_doublebw_vlsu
   logic     [NrInterfaces-1:0] vrf_commit_intf_valid, vrf_commit_intf_valid_q;
   logic     [NrInterfaces-1:0] resp_overlap;
 
+  // Some metadata tracking to handle small vector length scenario
+  commit_metadata_t commit_insn_q_rsp;
+  `FF(commit_insn_q_rsp, commit_insn_q, '0)
+
+  // Check if the vector length is small such that only one of the interface is participating,
+  // In this case bypass check for a valid response from the second interface
+  logic vrf_commit_bypass;
+  assign vrf_commit_bypass = commit_insn_q_rsp.vl <= ( NrMemPorts * ELENB / 2)  ? 1'b1 : 1'b0;
+
   for (genvar intf = 0; intf < NrInterfaces; intf++) begin : gen_vrf_req_register_intf
     spill_register #(
       .T(vrf_req_t)
@@ -675,12 +688,13 @@ module spatz_doublebw_vlsu
 
     // To track a valid response on an interface until both interfaces finish and can send to the VRF
     // When this happens the FF is cleared
-    // `FFLARNC(vrf_valid_rsp_q[intf], 1'b1, vrf_valid_rsp[intf], vlsu_rsp_valid_o & ~resp_overlap[intf], 1'b0, clk_i, rst_ni)
     assign vrf_valid_rsp_d[intf] = (vlsu_rsp_valid_o & ~resp_overlap[intf]) ? 1'b0 : (vrf_valid_rsp[intf] ? 1'b1 : vrf_valid_rsp_q[intf]);
     `FF(vrf_valid_rsp_q[intf], vrf_valid_rsp_d[intf], 1'b0)
 
+    // vrf_commit_intf_valid tracks if an interface is ready for completion
+    // If only one of the interface has completed, track the completion in vrf_commit_intf_valid_q
     // Check if either a previously tracked response or there is a response in the current cycle
-    assign vrf_commit_intf_valid[intf] = vrf_valid_rsp[intf] | vrf_valid_rsp_q[intf];
+    assign vrf_commit_intf_valid[intf] = vrf_valid_rsp[intf] | vrf_valid_rsp_q[intf] | (intf == 1 ? vrf_commit_bypass : 1'b0);
     `FF(vrf_commit_intf_valid_q[intf], vrf_commit_intf_valid[intf], 1'b0);
   end
 
@@ -694,11 +708,14 @@ module spatz_doublebw_vlsu
   // Check if interface 1 is the interface trying to commit, if so take resp information from interface 1
   // If both interfaces in sync, interface 1 is given priority
   assign resp_intf = vrf_commit_intf_valid_q [1] == 1'b0 ? 1'b1 : 1'b0;
+
+  // Check is both interfaces has reached to a completion and if the last write to the VRF is also done
+  // Assign the instruction id from the interface that completes the last
   assign vlsu_rsp_o = &vrf_commit_intf_valid && |vrf_req_valid_q ? vrf_req_q[resp_intf].rsp   : '{id: commit_insn_q.id, default: '0};
 
   // Send response back to the controller to indicate end of request
   // Check if both the interfaces have completed request and have a valid response to send
-  // Check if atleast one interface has a valid (interfaces can send responses asynchronously, but they finish the request together)
+  // Check if atleast one interface has a valid (interfaces can send responses asynchronously to the VRF)
   // Set reponse high if one of the interfaces has a ready indicating the response has been written to the VRF
   assign vlsu_rsp_valid_o = &vrf_commit_intf_valid && |vrf_req_valid_q ? |vrf_req_ready_q : vlsu_finished_req && !commit_insn_q.is_load;