Attempt to fix GL_TEST

Author: rejunity

test/Makefile

@@ -33,9 +33,9 @@ VERILOG_SOURCES += $(PWD)/gate_level_netlist.v
 endif
 
 # Include the testbench sources:
-VERILOG_SOURCES += $(PWD)/tb.v
-# VERILOG_SOURCES += $(PWD)/qspi_rom_emu.v # compilation error in IHP130 devcontainer
+VERILOG_SOURCES += $(PWD)/qspi_rom_emu.v
 # VERILOG_SOURCES += $(PWD)/macro_rom_emu.v # external ROMs are not supported with IHP130
+VERILOG_SOURCES += $(PWD)/tb.v
 TOPLEVEL = tb
 
 MODULE = test

test/qspi_rom_emu.v

@@ -20,6 +20,9 @@ module qspi_rom_emu #(parameter ADDR_BITS = 24) (
 
   reg [ADDR_BITS-1:0] addr; // read address
 
+  reg [15:0] data;
+  reg [7:0] rom [4095:0]; initial $readmemh("../roms/rom.mem", rom, 0, 4095);
+
   reg sclk_prev; always @(posedge clk) sclk_prev <= sclk;
   wire sclk_negedge = sclk_prev != sclk && !sclk;
   reg  [7:0] counter;
@@ -46,11 +49,9 @@ module qspi_rom_emu #(parameter ADDR_BITS = 24) (
     end
   end
 
-  reg [15:0] data;
-  reg [7:0] rom [4095:0];
-  initial begin
-    $readmemh("../roms/rom.mem", rom, 0, 4095);
-    // DEBUG: override reset vector
-    // rom[12'hFFD] <= 8'hF0; rom[12'hFFC] <= 8'h00;
-  end  
+  // // DEBUG: override reset vector
+  // initial begin
+  //  rom[12'hFFD] <= 8'hF0; rom[12'hFFC] <= 8'h00;
+  // end  
+
 endmodule

test/tb.v

@@ -24,6 +24,14 @@ module tb ();
   wire [7:0] uio_out;
   wire [7:0] uio_oe;
 
+  qspi_rom_emu qspi_rom_emu(
+    .clk        (clk),
+    .reset      (~rst_n),
+    .sclk       ( uio_out[3]),
+    .select     ( uio_out[0]),
+    .cmd_addr_in({uio_out[5:4], uio_out[2:1]}),
+    .data_out   ({ uio_in[5:4], uio_in [2:1]}));
+
   // Replace tt_um_example with your module name:
   tt_um_rejunity_atari2600 user_project (
       .ui_in  (ui_in),    // Dedicated inputs