From 790eb916393fcc0d1117d77f0b2c0c48e84b431c Mon Sep 17 00:00:00 2001 From: root Date: Tue, 30 Dec 2025 09:27:11 -0500 Subject: [PATCH 01/12] spike: add --pc-harts option for per-hart start addresses Currently, the --pc flag sets the entry point for all processors globally, or relies on the ELF entry point. This is insufficient for asymmetric multi-processing (AMP) setups or bare-metal RTL verification where different harts must begin execution at distinct physical addresses (e.g., Hart 0 at 0x2000, Hart 1 at 0x4000). This patch adds the --pc-harts= argument, allowing users to explicitly override the start PC for specific hart IDs. --- spike_main/spike.cc | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/spike_main/spike.cc b/spike_main/spike.cc index 5617a8254d..1936e33132 100644 --- a/spike_main/spike.cc +++ b/spike_main/spike.cc @@ -20,6 +20,7 @@ #include #include #include +#include #include "../VERSION" static void help(int exit_code = 1) @@ -46,6 +47,8 @@ static void help(int exit_code = 1) fprintf(stderr, " --pmpgranularity= PMP Granularity in bytes [default 4]\n"); fprintf(stderr, " --priv= RISC-V privilege modes supported [default %s]\n", DEFAULT_PRIV); fprintf(stderr, " --pc=
Override ELF entry point\n"); + fprintf(stderr, " --pc-harts= Override start PC for specific harts\n" + " (e.g. 0:0x2000,1:0x4000)\n"); fprintf(stderr, " --hartids= Explicitly specify hartids, default is 0,1,...\n"); fprintf(stderr, " --ic=:: Instantiate a cache model with S sets,\n"); fprintf(stderr, " --dc=:: W ways, and B-byte blocks (with S and\n"); @@ -347,6 +350,9 @@ int main(int argc, char** argv) cfg_t cfg; + //Map to store + std::map hart_start_pcs; + auto const device_parser = [&plugin_device_factories](const char *s) { const std::string device_args(s); std::vector parsed_args; @@ -382,6 +388,23 @@ int main(int argc, char** argv) parser.option(0, "halted", 0, [&](const char UNUSED *s){halted = true;}); parser.option(0, "rbb-port", 1, [&](const char* s){use_rbb = true; rbb_port = atoul_safe(s);}); parser.option(0, "pc", 1, [&](const char* s){cfg.start_pc = strtoull(s, 0, 0);}); + + parser.option(0, "pc-harts", 1, [&](const char* s){ + std::string arg(s); + std::stringstream ss(arg); + std::string pair; + while(std::getline(ss, pair, ',')) { + size_t delim = pair.find(':'); + if(delim == std::string::npos) { + fprintf(stderr, "Error: --pc-harts format is hartid:addr,hartid:addr\n"); + exit(1); + } + size_t hartid = std::stoul(pair.substr(0, delim)); + reg_t addr = std::strtoull(pair.substr(delim+1).c_str(), NULL, 0); + hart_start_pcs[hartid] = addr; + } + }); + parser.option(0, "hartids", 1, [&](const char* s){ cfg.hartids = parse_hartids(s); cfg.explicit_hartids = true; @@ -554,6 +577,14 @@ int main(int argc, char** argv) s.configure_log(log, log_commits); s.set_histogram(histogram); + for(size_t i = 0; i < cfg.nprocs(); i++) { + size_t hartid = cfg.hartids[i]; + + if(hart_start_pcs.count(hartid)){ + s.get_core(i)->get_state()->pc = hart_start_pcs[hartid]; + } + } + auto return_code = s.run(); for (auto& mem : mems) From b711d18a8a254199e3756012eb508f7c290e5767 Mon Sep 17 00:00:00 2001 From: Natheir Abu-Dahab <20204834+nabudahab@users.noreply.github.com> Date: Sun, 25 Jan 2026 23:12:45 -0500 Subject: [PATCH 02/12] Rename '--pc-harts' option to '--pcs' in spike.cc and fix formatting Signed-off-by: Natheir Abu-Dahab <20204834+nabudahab@users.noreply.github.com> --- spike_main/spike.cc | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/spike_main/spike.cc b/spike_main/spike.cc index e781f1f5d2..44105dd140 100644 --- a/spike_main/spike.cc +++ b/spike_main/spike.cc @@ -47,7 +47,7 @@ static void help(int exit_code = 1) fprintf(stderr, " --pmpgranularity= PMP Granularity in bytes [default 4]\n"); fprintf(stderr, " --priv= RISC-V privilege modes supported [default %s]\n", DEFAULT_PRIV); fprintf(stderr, " --pc=
Override ELF entry point\n"); - fprintf(stderr, " --pc-harts= Override start PC for specific harts\n" + fprintf(stderr, " --pcs= Override start PC for specific harts\n" " (e.g. 0:0x2000,1:0x4000)\n"); fprintf(stderr, " --hartids= Explicitly specify hartids, default is 0,1,...\n"); fprintf(stderr, " --ic=:: Instantiate a cache model with S sets,\n"); @@ -349,7 +349,6 @@ int main(int argc, char** argv) cfg_t cfg; - //Map to store std::map hart_start_pcs; auto const device_parser = [&plugin_device_factories](const char *s) { @@ -388,14 +387,14 @@ int main(int argc, char** argv) parser.option(0, "rbb-port", 1, [&](const char* s){use_rbb = true; rbb_port = atoul_safe(s);}); parser.option(0, "pc", 1, [&](const char* s){cfg.start_pc = strtoull(s, 0, 0);}); - parser.option(0, "pc-harts", 1, [&](const char* s){ + parser.option(0, "pcs", 1, [&](const char* s){ std::string arg(s); std::stringstream ss(arg); std::string pair; while(std::getline(ss, pair, ',')) { size_t delim = pair.find(':'); if(delim == std::string::npos) { - fprintf(stderr, "Error: --pc-harts format is hartid:addr,hartid:addr\n"); + fprintf(stderr, "Error: --pcs format is hartid:addr,hartid:addr\n"); exit(1); } size_t hartid = std::stoul(pair.substr(0, delim)); @@ -575,10 +574,10 @@ int main(int argc, char** argv) s.configure_log(log, log_commits); s.set_histogram(histogram); - for(size_t i = 0; i < cfg.nprocs(); i++) { + for (size_t i = 0; i < cfg.nprocs(); i++) { size_t hartid = cfg.hartids[i]; - if(hart_start_pcs.count(hartid)){ + if (hart_start_pcs.count(hartid)){ s.get_core(i)->get_state()->pc = hart_start_pcs[hartid]; } } From ea6a854f1761b5660b00bc0e6a26f87f685c0c20 Mon Sep 17 00:00:00 2001 From: Natheir Abu-Dahab <20204834+nabudahab@users.noreply.github.com> Date: Mon, 26 Jan 2026 23:51:51 -0500 Subject: [PATCH 03/12] Update spike_main/spike.cc Co-authored-by: Jerry Zhao Signed-off-by: Natheir Abu-Dahab <20204834+nabudahab@users.noreply.github.com> --- spike_main/spike.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/spike_main/spike.cc b/spike_main/spike.cc index 44105dd140..0b1d3bd8ac 100644 --- a/spike_main/spike.cc +++ b/spike_main/spike.cc @@ -391,7 +391,7 @@ int main(int argc, char** argv) std::string arg(s); std::stringstream ss(arg); std::string pair; - while(std::getline(ss, pair, ',')) { + while (std::getline(ss, pair, ',')) { size_t delim = pair.find(':'); if(delim == std::string::npos) { fprintf(stderr, "Error: --pcs format is hartid:addr,hartid:addr\n"); From 2c9a342f9cc2b2c886b3f0c5e968363201d1c763 Mon Sep 17 00:00:00 2001 From: Natheir Abu-Dahab <20204834+nabudahab@users.noreply.github.com> Date: Mon, 26 Jan 2026 23:52:16 -0500 Subject: [PATCH 04/12] Update spike_main/spike.cc fix formatting Co-authored-by: Jerry Zhao Signed-off-by: Natheir Abu-Dahab <20204834+nabudahab@users.noreply.github.com> --- spike_main/spike.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/spike_main/spike.cc b/spike_main/spike.cc index 0b1d3bd8ac..0ae460a2e8 100644 --- a/spike_main/spike.cc +++ b/spike_main/spike.cc @@ -393,7 +393,7 @@ int main(int argc, char** argv) std::string pair; while (std::getline(ss, pair, ',')) { size_t delim = pair.find(':'); - if(delim == std::string::npos) { + if (delim == std::string::npos) { fprintf(stderr, "Error: --pcs format is hartid:addr,hartid:addr\n"); exit(1); } From 71096c02a529efb92b68d98988c3221016452301 Mon Sep 17 00:00:00 2001 From: Natheir Abu-Dahab <20204834+nabudahab@users.noreply.github.com> Date: Mon, 26 Jan 2026 23:54:45 -0500 Subject: [PATCH 05/12] Fix formatting of help message for --pcs option Fix implemented as suggested by @jerryz123 Signed-off-by: Natheir Abu-Dahab <20204834+nabudahab@users.noreply.github.com> --- spike_main/spike.cc | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/spike_main/spike.cc b/spike_main/spike.cc index 0ae460a2e8..436e8d94ab 100644 --- a/spike_main/spike.cc +++ b/spike_main/spike.cc @@ -47,8 +47,7 @@ static void help(int exit_code = 1) fprintf(stderr, " --pmpgranularity= PMP Granularity in bytes [default 4]\n"); fprintf(stderr, " --priv= RISC-V privilege modes supported [default %s]\n", DEFAULT_PRIV); fprintf(stderr, " --pc=
Override ELF entry point\n"); - fprintf(stderr, " --pcs= Override start PC for specific harts\n" - " (e.g. 0:0x2000,1:0x4000)\n"); + fprintf(stderr, " --pcs= Override start PC for specific harts\n"); fprintf(stderr, " --hartids= Explicitly specify hartids, default is 0,1,...\n"); fprintf(stderr, " --ic=:: Instantiate a cache model with S sets,\n"); fprintf(stderr, " --dc=:: W ways, and B-byte blocks (with S and\n"); From df4d99e221860720d59ba27e2a885de972fcc841 Mon Sep 17 00:00:00 2001 From: nabudahab Date: Wed, 28 Jan 2026 19:04:10 -0500 Subject: [PATCH 06/12] adjust cfg.start_pc to handle the hart-specialized start_pc case --- riscv/cfg.h | 29 ++++++++++++++++++++++++++++- riscv/processor.cc | 3 ++- riscv/sim.cc | 3 ++- spike_main/spike.cc | 6 +++--- 4 files changed, 35 insertions(+), 6 deletions(-) diff --git a/riscv/cfg.h b/riscv/cfg.h index 779634e98b..1a06e5eb93 100644 --- a/riscv/cfg.h +++ b/riscv/cfg.h @@ -6,6 +6,7 @@ #include #include "decode.h" #include +#include class abstract_sim_if_t; typedef enum { @@ -59,6 +60,32 @@ class mem_cfg_t reg_t size; }; +class start_pc_t +{ +public: + void set_global(reg_t pc) { + global_pc = pc; + } + + void set_override(size_t hart_id, reg_t pc) { + hart_pcs[hart_id] = pc; + } + + std::optional get(size_t hart_id) const { + auto it = hart_pcs.find(hart_id); + + if (it != hart_pcs.end()) { + return it->second; + } else { + return global_pc; + } + } + +private: + std::optional global_pc; + std::map hart_pcs; +}; + class cfg_t { public: @@ -72,7 +99,7 @@ class cfg_t reg_t pmpregions; reg_t pmpgranularity; std::vector mem_layout; - std::optional start_pc; + start_pc_t start_pc; std::vector hartids; bool explicit_hartids; bool real_time_clint; diff --git a/riscv/processor.cc b/riscv/processor.cc index 80a47d9342..f394fa9c27 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -167,8 +167,9 @@ void processor_t::reset() e.second->reset(*this); } - if (sim) + if (sim) { sim->proc_reset(id); + } } extension_t* processor_t::get_extension() diff --git a/riscv/sim.cc b/riscv/sim.cc index 7b07bd67e2..7d3fe46f8f 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -360,7 +360,7 @@ void sim_t::set_rom() { const int reset_vec_size = 8; - reg_t start_pc = cfg->start_pc.value_or(get_entry_point()); + reg_t start_pc = cfg->start_pc.get(0).value_or(get_entry_point()); uint32_t reset_vec[reset_vec_size] = { 0x297, // auipc t0,0x0 @@ -479,4 +479,5 @@ endianness_t sim_t::get_target_endianness() const void sim_t::proc_reset(unsigned id) { debug_module.proc_reset(id); + procs[id] -> get_state() -> pc = cfg->start_pc.get(id).value_or(get_entry_point()); } diff --git a/spike_main/spike.cc b/spike_main/spike.cc index 436e8d94ab..8baf36dac8 100644 --- a/spike_main/spike.cc +++ b/spike_main/spike.cc @@ -384,7 +384,7 @@ int main(int argc, char** argv) parser.option('m', 0, 1, [&](const char* s){cfg.mem_layout = parse_mem_layout(s);}); parser.option(0, "halted", 0, [&](const char UNUSED *s){halted = true;}); parser.option(0, "rbb-port", 1, [&](const char* s){use_rbb = true; rbb_port = atoul_safe(s);}); - parser.option(0, "pc", 1, [&](const char* s){cfg.start_pc = strtoull(s, 0, 0);}); + parser.option(0, "pc", 1, [&](const char* s){cfg.start_pc.set_global(strtoull(s, 0, 0));}); parser.option(0, "pcs", 1, [&](const char* s){ std::string arg(s); @@ -398,7 +398,7 @@ int main(int argc, char** argv) } size_t hartid = std::stoul(pair.substr(0, delim)); reg_t addr = std::strtoull(pair.substr(delim+1).c_str(), NULL, 0); - hart_start_pcs[hartid] = addr; + cfg.start_pc.set_override(hartid, addr); } }); @@ -576,7 +576,7 @@ int main(int argc, char** argv) for (size_t i = 0; i < cfg.nprocs(); i++) { size_t hartid = cfg.hartids[i]; - if (hart_start_pcs.count(hartid)){ + if (hart_start_pcs.count(hartid)) { s.get_core(i)->get_state()->pc = hart_start_pcs[hartid]; } } From 8d76f0a4afc2f312412b33b4c5edda7acec8b74e Mon Sep 17 00:00:00 2001 From: nabudahab Date: Thu, 29 Jan 2026 10:27:46 -0500 Subject: [PATCH 07/12] fix segfault caused by proc_reset being called before procs is fully populated --- riscv/sim.cc | 3 ++- spike_main/spike.cc | 10 ++-------- 2 files changed, 4 insertions(+), 9 deletions(-) diff --git a/riscv/sim.cc b/riscv/sim.cc index 7d3fe46f8f..26a19c727f 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -479,5 +479,6 @@ endianness_t sim_t::get_target_endianness() const void sim_t::proc_reset(unsigned id) { debug_module.proc_reset(id); - procs[id] -> get_state() -> pc = cfg->start_pc.get(id).value_or(get_entry_point()); + if(id < procs.size()) + procs[id] -> get_state() -> pc = cfg->start_pc.get(id).value_or(get_entry_point()); } diff --git a/spike_main/spike.cc b/spike_main/spike.cc index 8baf36dac8..afb970650c 100644 --- a/spike_main/spike.cc +++ b/spike_main/spike.cc @@ -348,7 +348,6 @@ int main(int argc, char** argv) cfg_t cfg; - std::map hart_start_pcs; auto const device_parser = [&plugin_device_factories](const char *s) { const std::string device_args(s); @@ -539,6 +538,7 @@ int main(int argc, char** argv) cfg.hartids = default_hartids; } + fprintf(stderr, "DEBUG: Constructing sim_t\n"); sim_t s(&cfg, halted, mems, plugin_device_factories, htif_args, dm_config, log_path, dtb_enabled, dtb_file, socket, @@ -573,14 +573,8 @@ int main(int argc, char** argv) s.configure_log(log, log_commits); s.set_histogram(histogram); - for (size_t i = 0; i < cfg.nprocs(); i++) { - size_t hartid = cfg.hartids[i]; - - if (hart_start_pcs.count(hartid)) { - s.get_core(i)->get_state()->pc = hart_start_pcs[hartid]; - } - } + fprintf(stderr, "DEBUG: Starting simulation\n"); auto return_code = s.run(); for (auto& mem : mems) From 41fd53bb493dac49218508bea9459b28406c88f1 Mon Sep 17 00:00:00 2001 From: nabudahab Date: Thu, 29 Jan 2026 10:42:30 -0500 Subject: [PATCH 08/12] align formatting --- riscv/sim.cc | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/riscv/sim.cc b/riscv/sim.cc index 26a19c727f..80b8e0c9d2 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -479,6 +479,8 @@ endianness_t sim_t::get_target_endianness() const void sim_t::proc_reset(unsigned id) { debug_module.proc_reset(id); - if(id < procs.size()) - procs[id] -> get_state() -> pc = cfg->start_pc.get(id).value_or(get_entry_point()); + if (id < procs.size()) { + procs[id]->get_state()->pc = + cfg->start_pc.get(id).value_or(get_entry_point()); + } } From c1990c95fea3a08cb3c38fe97a5df03b77a5fb6d Mon Sep 17 00:00:00 2001 From: nabudahab Date: Thu, 29 Jan 2026 10:54:21 -0500 Subject: [PATCH 09/12] code cleanup --- riscv/processor.cc | 3 +-- spike_main/spike.cc | 2 -- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/riscv/processor.cc b/riscv/processor.cc index f394fa9c27..80a47d9342 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -167,9 +167,8 @@ void processor_t::reset() e.second->reset(*this); } - if (sim) { + if (sim) sim->proc_reset(id); - } } extension_t* processor_t::get_extension() diff --git a/spike_main/spike.cc b/spike_main/spike.cc index afb970650c..c44aabac50 100644 --- a/spike_main/spike.cc +++ b/spike_main/spike.cc @@ -538,7 +538,6 @@ int main(int argc, char** argv) cfg.hartids = default_hartids; } - fprintf(stderr, "DEBUG: Constructing sim_t\n"); sim_t s(&cfg, halted, mems, plugin_device_factories, htif_args, dm_config, log_path, dtb_enabled, dtb_file, socket, @@ -574,7 +573,6 @@ int main(int argc, char** argv) s.set_histogram(histogram); - fprintf(stderr, "DEBUG: Starting simulation\n"); auto return_code = s.run(); for (auto& mem : mems) From b5f47319d1196a51ca0e5262d481e31e16f8ffa8 Mon Sep 17 00:00:00 2001 From: Natheir Abu-Dahab <20204834+nabudahab@users.noreply.github.com> Date: Thu, 29 Jan 2026 11:01:48 -0500 Subject: [PATCH 10/12] Remove blank lines in spike.cc Removed unnecessary blank lines for cleaner code. Signed-off-by: Natheir Abu-Dahab <20204834+nabudahab@users.noreply.github.com> --- spike_main/spike.cc | 2 -- 1 file changed, 2 deletions(-) diff --git a/spike_main/spike.cc b/spike_main/spike.cc index c44aabac50..54497efc1f 100644 --- a/spike_main/spike.cc +++ b/spike_main/spike.cc @@ -348,7 +348,6 @@ int main(int argc, char** argv) cfg_t cfg; - auto const device_parser = [&plugin_device_factories](const char *s) { const std::string device_args(s); std::vector parsed_args; @@ -572,7 +571,6 @@ int main(int argc, char** argv) s.configure_log(log, log_commits); s.set_histogram(histogram); - auto return_code = s.run(); for (auto& mem : mems) From fab6dc3f51ad6e856bf18b158d60a89869cf0791 Mon Sep 17 00:00:00 2001 From: nabudahab Date: Sat, 31 Jan 2026 22:47:20 -0500 Subject: [PATCH 11/12] move implementations of start_pc class functions to cfg.cc from cfg.h --- riscv/cfg.cc | 21 +++++++++++++++++++++ riscv/cfg.h | 18 +++--------------- 2 files changed, 24 insertions(+), 15 deletions(-) diff --git a/riscv/cfg.cc b/riscv/cfg.cc index 794e955598..e546fca38d 100644 --- a/riscv/cfg.cc +++ b/riscv/cfg.cc @@ -48,3 +48,24 @@ cfg_t::cfg_t() trigger_count = 4; cache_blocksz = 64; } + +void start_pc_t::set_global(reg_t pc) +{ + global_pc = pc; +} + +void start_pc_t::set_override(size_t hart_id, reg_t pc) +{ + hart_pcs[hart_id] = pc; +} + +std::optional start_pc_t::get(size_t hart_id) const +{ + auto it = hart_pcs.find(hart_id); + + if (it != hart_pcs.end()) { + return it->second; + } else { + return global_pc; + } +} diff --git a/riscv/cfg.h b/riscv/cfg.h index 1a06e5eb93..ea3219ad4e 100644 --- a/riscv/cfg.h +++ b/riscv/cfg.h @@ -63,23 +63,11 @@ class mem_cfg_t class start_pc_t { public: - void set_global(reg_t pc) { - global_pc = pc; - } - - void set_override(size_t hart_id, reg_t pc) { - hart_pcs[hart_id] = pc; - } + void set_global(reg_t pc); - std::optional get(size_t hart_id) const { - auto it = hart_pcs.find(hart_id); + void set_override(size_t hart_id, reg_t pc); - if (it != hart_pcs.end()) { - return it->second; - } else { - return global_pc; - } - } + std::optional get(size_t hart_id) const; private: std::optional global_pc; From 24b27ebab267994155e997e00b809693dd142b83 Mon Sep 17 00:00:00 2001 From: nabudahab Date: Tue, 10 Feb 2026 19:25:35 -0500 Subject: [PATCH 12/12] Fix default to RSTVEC logic in sim_t::proc_reset() --- riscv/sim.cc | 242 +++++++++++++++++++++++++++++++-------------------- 1 file changed, 146 insertions(+), 96 deletions(-) diff --git a/riscv/sim.cc b/riscv/sim.cc index 80b8e0c9d2..3c07091afa 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -32,52 +32,54 @@ static void handle_signal(int sig) const size_t sim_t::INTERLEAVE; -extern device_factory_t* clint_factory; -extern device_factory_t* plic_factory; -extern device_factory_t* ns16550_factory; +extern device_factory_t *clint_factory; +extern device_factory_t *plic_factory; +extern device_factory_t *ns16550_factory; sim_t::sim_t(const cfg_t *cfg, bool halted, - std::vector> mems, - const std::vector& plugin_device_factories, - const std::vector& args, + std::vector> mems, + const std::vector &plugin_device_factories, + const std::vector &args, const debug_module_config_t &dm_config, const char *log_path, bool dtb_enabled, const char *dtb_file, bool socket_enabled, FILE *cmd_file, // needed for command line option --cmd std::optional instruction_limit) - : htif_t(args), - cfg(cfg), - mems(mems), - dtb_enabled(dtb_enabled), - log_file(log_path), - cmd_file(cmd_file), - instruction_limit(instruction_limit), - sout_(nullptr), - current_step(0), - current_proc(0), - debug(false), - histogram_enabled(false), - log(false), - remote_bitbang(NULL), - debug_module(this, dm_config) + : htif_t(args), + cfg(cfg), + mems(mems), + dtb_enabled(dtb_enabled), + log_file(log_path), + cmd_file(cmd_file), + instruction_limit(instruction_limit), + sout_(nullptr), + current_step(0), + current_proc(0), + debug(false), + histogram_enabled(false), + log(false), + remote_bitbang(NULL), + debug_module(this, dm_config) { signal(SIGINT, &handle_signal); sout_.rdbuf(std::cerr.rdbuf()); // debug output goes to stderr by default - for (auto& x : mems) + for (auto &x : mems) bus.add_device(x.first, x.second); bus.add_device(DEBUG_START, &debug_module); socketif = NULL; #ifdef HAVE_BOOST_ASIO - if (socket_enabled) { + if (socket_enabled) + { socketif = new socketif_t(); } #else - if (socket_enabled) { + if (socket_enabled) + { fputs("Socket support requires compilation with boost asio; " "please rebuild the riscv-isa-sim project using " "\"configure --with-boost-asio\".\n", @@ -87,7 +89,8 @@ sim_t::sim_t(const cfg_t *cfg, bool halted, #endif #ifndef RISCV_ENABLE_DUAL_ENDIAN - if (cfg->endianness != endianness_little) { + if (cfg->endianness != endianness_little) + { fputs("Big-endian support has not been properly enabled; " "please rebuild the riscv-isa-sim project using " "\"configure --enable-dual-endian\".\n", @@ -99,8 +102,10 @@ sim_t::sim_t(const cfg_t *cfg, bool halted, debug_mmu = new mmu_t(this, cfg->endianness, NULL, cfg->cache_blocksz); // When running without using a dtb, skip the fdt-based configuration steps - if (!dtb_enabled) { - for (size_t i = 0; i < cfg->nprocs(); i++) { + if (!dtb_enabled) + { + for (size_t i = 0; i < cfg->nprocs(); i++) + { procs.push_back(new processor_t(cfg->isa, cfg->priv, cfg, this, cfg->hartids[i], halted, log_file.get(), sout_)); @@ -118,28 +123,33 @@ sim_t::sim_t(const cfg_t *cfg, bool halted, // particular, the default device tree configuration that you get without // setting the dtb_file argument has one. std::vector device_factories = { - {clint_factory, {}}, - {plic_factory, {}}, - {ns16550_factory, {}}}; + {clint_factory, {}}, + {plic_factory, {}}, + {ns16550_factory, {}}}; device_factories.insert(device_factories.end(), plugin_device_factories.begin(), plugin_device_factories.end()); // Load dtb_file if provided, otherwise self-generate a dts/dtb - if (dtb_file) { + if (dtb_file) + { std::ifstream fin(dtb_file, std::ios::binary); - if (!fin.good()) { + if (!fin.good()) + { std::cerr << "can't find dtb file: " << dtb_file << std::endl; exit(-1); } std::stringstream strstream; strstream << fin.rdbuf(); dtb = strstream.str(); - } else { + } + else + { std::string device_nodes; - for (const device_factory_sargs_t& factory_sargs: device_factories) { - const device_factory_t* factory = factory_sargs.first; - const std::vector& sargs = factory_sargs.second; + for (const device_factory_sargs_t &factory_sargs : device_factories) + { + const device_factory_t *factory = factory_sargs.first; + const std::vector &sargs = factory_sargs.second; device_nodes.append(factory->generate_dts(this, sargs)); } dts = make_dts(INSNS_PER_RTC_TICK, CPU_HZ, cfg, mems, device_nodes); @@ -147,11 +157,15 @@ sim_t::sim_t(const cfg_t *cfg, bool halted, } int fdt_code = fdt_check_header(dtb.c_str()); - if (fdt_code) { + if (fdt_code) + { std::cerr << "Failed to read DTB from "; - if (!dtb_file) { + if (!dtb_file) + { std::cerr << "auto-generated DTS string"; - } else { + } + else + { std::cerr << "`" << dtb_file << "'"; } std::cerr << ": " << fdt_strerror(fdt_code) << ".\n"; @@ -169,20 +183,23 @@ sim_t::sim_t(const cfg_t *cfg, bool halted, return; for (cpu_offset = fdt_get_first_subnode(fdt, cpu_offset); cpu_offset >= 0; - cpu_offset = fdt_get_next_subnode(fdt, cpu_offset)) { + cpu_offset = fdt_get_next_subnode(fdt, cpu_offset)) + { if (!(cpu_map_offset < 0) && cpu_offset == cpu_map_offset) continue; - if (cpu_idx != procs.size()) { + if (cpu_idx != procs.size()) + { std::cerr << "Spike only supports contiguous CPU IDs in the DTS" << std::endl; exit(1); } // handle isa string - const char* isa_str; + const char *isa_str; rc = fdt_parse_isa(fdt, cpu_offset, &isa_str); - if (rc != 0) { + if (rc != 0) + { std::cerr << "core (" << cpu_idx << ") has an invalid or missing 'riscv,isa'\n"; exit(1); } @@ -190,7 +207,8 @@ sim_t::sim_t(const cfg_t *cfg, bool halted, // handle hartid uint32_t hartid; rc = fdt_parse_hartid(fdt, cpu_offset, &hartid); - if (rc != 0) { + if (rc != 0) + { std::cerr << "core (" << cpu_idx << ") has an invalid or missing `reg` (hartid)\n"; exit(1); } @@ -206,7 +224,8 @@ sim_t::sim_t(const cfg_t *cfg, bool halted, pmp_num = 0; procs[cpu_idx]->set_pmp_num(pmp_num); - if (fdt_parse_pmp_alignment(fdt, cpu_offset, &pmp_granularity) == 0) { + if (fdt_parse_pmp_alignment(fdt, cpu_offset, &pmp_granularity) == 0) + { procs[cpu_idx]->set_pmp_granularity(pmp_granularity); } @@ -214,18 +233,30 @@ sim_t::sim_t(const cfg_t *cfg, bool halted, const char *mmu_type; rc = fdt_parse_mmu_type(fdt, cpu_offset, &mmu_type); procs[cpu_idx]->set_max_vaddr_bits(0); - if (rc == 0) { - if (strncmp(mmu_type, "riscv,sv32", strlen("riscv,sv32")) == 0) { + if (rc == 0) + { + if (strncmp(mmu_type, "riscv,sv32", strlen("riscv,sv32")) == 0) + { procs[cpu_idx]->set_max_vaddr_bits(32); - } else if (strncmp(mmu_type, "riscv,sv39", strlen("riscv,sv39")) == 0) { + } + else if (strncmp(mmu_type, "riscv,sv39", strlen("riscv,sv39")) == 0) + { procs[cpu_idx]->set_max_vaddr_bits(39); - } else if (strncmp(mmu_type, "riscv,sv48", strlen("riscv,sv48")) == 0) { + } + else if (strncmp(mmu_type, "riscv,sv48", strlen("riscv,sv48")) == 0) + { procs[cpu_idx]->set_max_vaddr_bits(48); - } else if (strncmp(mmu_type, "riscv,sv57", strlen("riscv,sv57")) == 0) { + } + else if (strncmp(mmu_type, "riscv,sv57", strlen("riscv,sv57")) == 0) + { procs[cpu_idx]->set_max_vaddr_bits(57); - } else if (strncmp(mmu_type, "riscv,sbare", strlen("riscv,sbare")) == 0) { + } + else if (strncmp(mmu_type, "riscv,sbare", strlen("riscv,sbare")) == 0) + { // has been set in the beginning - } else { + } + else + { std::cerr << "core (" << cpu_idx << ") has an invalid 'mmu-type': " @@ -240,22 +271,26 @@ sim_t::sim_t(const cfg_t *cfg, bool halted, } // must be located after procs/harts are set (devices might use sim_t get_* member functions) - for (size_t i = 0; i < device_factories.size(); i++) { - const device_factory_t* factory = device_factories[i].first; - const std::vector& sargs = device_factories[i].second; + for (size_t i = 0; i < device_factories.size(); i++) + { + const device_factory_t *factory = device_factories[i].first; + const std::vector &sargs = device_factories[i].second; reg_t device_base = 0; - abstract_device_t* device = factory->parse_from_fdt(fdt, this, &device_base, sargs); - if (device) { + abstract_device_t *device = factory->parse_from_fdt(fdt, this, &device_base, sargs); + if (device) + { assert(device_base); std::shared_ptr dev_ptr(device); add_device(device_base, dev_ptr); - if (dynamic_cast(&*dev_ptr)) { + if (dynamic_cast(&*dev_ptr)) + { assert(!clint); clint = std::static_pointer_cast(dev_ptr); } - if (dynamic_cast(&*dev_ptr)) { + if (dynamic_cast(&*dev_ptr)) + { assert(!plic); plic = std::static_pointer_cast(dev_ptr); } @@ -294,19 +329,23 @@ void sim_t::step(size_t n) { current_step = 0; procs[current_proc]->get_mmu()->yield_load_reservation(); - if (++current_proc == procs.size()) { + if (++current_proc == procs.size()) + { current_proc = 0; reg_t rtc_ticks = INTERLEAVE / INSNS_PER_RTC_TICK; - for (auto &dev : devices) dev->tick(rtc_ticks); + for (auto &dev : devices) + dev->tick(rtc_ticks); } } } } -const char* sim_t::get_dts() { +const char *sim_t::get_dts() +{ dts = dtb_to_dts(dtb); - return dts.c_str(); + return dts.c_str(); } -void sim_t::add_device(reg_t addr, std::shared_ptr dev) { +void sim_t::add_device(reg_t addr, std::shared_ptr dev) +{ bus.add_device(addr, dev.get()); devices.push_back(dev); } @@ -319,7 +358,8 @@ void sim_t::set_debug(bool value) void sim_t::set_histogram(bool value) { histogram_enabled = value; - for (size_t i = 0; i < procs.size(); i++) { + for (size_t i = 0; i < procs.size(); i++) + { procs[i]->set_histogram(histogram_enabled); } } @@ -331,25 +371,26 @@ void sim_t::configure_log(bool enable_log, bool enable_commitlog) if (!enable_commitlog) return; - for (processor_t *proc : procs) { + for (processor_t *proc : procs) + { proc->enable_log_commits(); } } void sim_t::set_procs_debug(bool value) { - for (size_t i=0; i< procs.size(); i++) + for (size_t i = 0; i < procs.size(); i++) procs[i]->set_debug(value); } -bool sim_t::mmio_load(reg_t paddr, size_t len, uint8_t* bytes) +bool sim_t::mmio_load(reg_t paddr, size_t len, uint8_t *bytes) { if (paddr + len < paddr) return false; return bus.load(paddr, len, bytes); } -bool sim_t::mmio_store(reg_t paddr, size_t len, const uint8_t* bytes) +bool sim_t::mmio_store(reg_t paddr, size_t len, const uint8_t *bytes) { if (paddr + len < paddr) return false; @@ -363,18 +404,17 @@ void sim_t::set_rom() reg_t start_pc = cfg->start_pc.get(0).value_or(get_entry_point()); uint32_t reset_vec[reset_vec_size] = { - 0x297, // auipc t0,0x0 - 0x28593 + (reset_vec_size * 4 << 20), // addi a1, t0, &dtb - 0xf1402573, // csrr a0, mhartid - get_core(0)->get_xlen() == 32 ? - 0x0182a283u : // lw t0,24(t0) - 0x0182b283u, // ld t0,24(t0) - 0x28067, // jr t0 - 0, - (uint32_t) (start_pc & 0xffffffff), - (uint32_t) (start_pc >> 32) - }; - if (get_target_endianness() == endianness_big) { + 0x297, // auipc t0,0x0 + 0x28593 + (reset_vec_size * 4 << 20), // addi a1, t0, &dtb + 0xf1402573, // csrr a0, mhartid + get_core(0)->get_xlen() == 32 ? 0x0182a283u : // lw t0,24(t0) + 0x0182b283u, // ld t0,24(t0) + 0x28067, // jr t0 + 0, + (uint32_t)(start_pc & 0xffffffff), + (uint32_t)(start_pc >> 32)}; + if (get_target_endianness() == endianness_big) + { int i; // Instuctions are little endian for (i = 0; reset_vec[i] != 0; i++) @@ -385,13 +425,15 @@ void sim_t::set_rom() // Correct the high/low order of 64-bit start PC if (get_core(0)->get_xlen() != 32) - std::swap(reset_vec[reset_vec_size-2], reset_vec[reset_vec_size-1]); - } else { + std::swap(reset_vec[reset_vec_size - 2], reset_vec[reset_vec_size - 1]); + } + else + { for (int i = 0; i < reset_vec_size; i++) reset_vec[i] = to_le(reset_vec[i]); } - std::vector rom((char*)reset_vec, (char*)reset_vec + sizeof(reset_vec)); + std::vector rom((char *)reset_vec, (char *)reset_vec + sizeof(reset_vec)); rom.insert(rom.end(), dtb.begin(), dtb.end()); const int align = 0x1000; @@ -401,7 +443,8 @@ void sim_t::set_rom() add_device(DEFAULT_RSTVEC, boot_rom); } -char* sim_t::addr_to_mem(reg_t paddr) { +char *sim_t::addr_to_mem(reg_t paddr) +{ auto page_offset = paddr % PGSIZE; auto page_addr = paddr - page_offset; @@ -409,7 +452,8 @@ char* sim_t::addr_to_mem(reg_t paddr) { return it->second + page_offset; auto desc = bus.find_device(page_addr, PGSIZE); - if (auto mem = dynamic_cast(desc.second)) { + if (auto mem = dynamic_cast(desc.second)) + { auto res = mem->contents(page_addr - desc.first); addr_to_mem_cache.insert({page_addr, res}); return res + page_offset; @@ -418,7 +462,7 @@ char* sim_t::addr_to_mem(reg_t paddr) { return nullptr; } -const char* sim_t::get_symbol(uint64_t paddr) +const char *sim_t::get_symbol(uint64_t paddr) { return htif_t::get_symbol(paddr); } @@ -438,9 +482,12 @@ void sim_t::idle() if (debug || ctrlc_pressed) interactive(); - else { - if (instruction_limit.has_value()) { - if (*instruction_limit < INTERLEAVE) { + else + { + if (instruction_limit.has_value()) + { + if (*instruction_limit < INTERLEAVE) + { // Final step. step(*instruction_limit); htif_exit(0); @@ -456,14 +503,14 @@ void sim_t::idle() remote_bitbang->tick(); } -void sim_t::read_chunk(addr_t taddr, size_t len, void* dst) +void sim_t::read_chunk(addr_t taddr, size_t len, void *dst) { assert(len == 8); auto data = debug_mmu->to_target(debug_mmu->load(taddr)); memcpy(dst, &data, sizeof data); } -void sim_t::write_chunk(addr_t taddr, size_t len, const void* src) +void sim_t::write_chunk(addr_t taddr, size_t len, const void *src) { assert(len == 8); target_endian data; @@ -473,14 +520,17 @@ void sim_t::write_chunk(addr_t taddr, size_t len, const void* src) endianness_t sim_t::get_target_endianness() const { - return debug_mmu->is_target_big_endian()? endianness_big : endianness_little; + return debug_mmu->is_target_big_endian() ? endianness_big : endianness_little; } void sim_t::proc_reset(unsigned id) { debug_module.proc_reset(id); - if (id < procs.size()) { - procs[id]->get_state()->pc = - cfg->start_pc.get(id).value_or(get_entry_point()); + if (id < procs.size()) + { + if (auto pc = cfg->start_pc.get(id)) + { + procs[id]->get_state()->pc = *pc; + } } }