use HLS to transfor CPP to Verilog #6
Description
Hello , I use Vivado 2020.1 to transfor urs CPP code to Verilog IP. But when i synthesis it , in the code named ldpcDec, the IDE always said that:"WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'minfo[0].V' (../src_c/hls_ldpc_dec-master/ldpcDec.cpp:20).
", and if i delete it , it alse cloudn't create to be an IP. I just began to study FPGA exploiting, I wish u can help me