Why is 'cycles_sr[9]' used as part of the 'READ_ST'.

[CraigBRS]

I don't understand the section below. Why is 'cycles_sr[9]' used ? Isn't the minimum delay only 3 cycles ? So why is the bit index '9' used ?

 if (state == READ_ST)  begin
     if (cycles_sr[3]) begin
         // command sent, now wait for result
         dq_oen <= 1;
     end
     if (cycles_sr[9])
         wait_for_rd_data <= 1;
     if (wait_for_rd_data && (rwds_in_ris ^ rwds_in_fal)) begin     // sample rwds falling edge to get a word / \_
         dout <= {dq_in_ris, dq_in_fal};
         ram_cs_n <= 1;
         ck_e <= 0;
         state <= IDLE_ST;
     end
 end

@zf3