Skip to content
View 5hy21am's full-sized avatar
0 followers · 25 following

Block or report 5hy21am

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
5hy21am/README.md

Hi There

👋 Hi, I’m Shyam Kumar.

🎓 Electronics Graduate.

🚩 Learning SoC Integration and AMBA protocols.

👀 I’m into RTL design, digital design, functional safety and vlsi design.

😄 I love exploring and learning new skills as well as implement those in my projects.

📫 Feel free to reach me: ks995515@gmail.com.

Popular repositories Loading

  1. 5hy21am 5hy21am Public

    Config files for my GitHub profile.

  2. https-github.com-5hy21am-verilog-examples https-github.com-5hy21am-verilog-examples Public

    Verilog

  3. https-github.com-5hy21am-VLSI-Fundamentals-Education-Kit https-github.com-5hy21am-VLSI-Fundamentals-Education-Kit Public

    HTML

  4. https-github.com-5hy21am-Introduction-to-SoC-Design-Education-Kit https-github.com-5hy21am-Introduction-to-SoC-Design-Education-Kit Public

    HTML

  5. https-github.com-5hy21am-skid_buffer https-github.com-5hy21am-skid_buffer Public

    SystemVerilog

  6. https-github.com-5hy21am-debouncer https-github.com-5hy21am-debouncer Public

    SystemVerilog