[Do not merge] Example Circuits and Customizations for DEMO

align/cmdline.py

@@ -52,7 +52,7 @@ def __init__(self, *args, **kwargs):
         parser.add_argument("-n",
                             "--nvariants",
                             type=int,
-                            default=1,
+                            default=4,
                             help='Number of layout candidates to (attempt to) generate')
         parser.add_argument("-e",
                             "--effort",
@@ -102,7 +102,7 @@ def __init__(self, *args, **kwargs):
 
         parser.add_argument('--router_mode',
                             type=str,
-                            default='top_down',
+                            default='bottom_up',
                             choices=['top_down','bottom_up','no_op'],
                             help='Router mode')
 
@@ -111,7 +111,7 @@ def __init__(self, *args, **kwargs):
                             help='Run in GUI mode')
 
         parser.add_argument('--skipGDS',
-                            action='store_true',
+                            action='store_false',
                             help='Don\'t generate GDS files.')
 
         parser.add_argument('--lambda_coeff',

align/compiler/find_constraint.py

@@ -472,8 +472,8 @@ def filter_symnet_const(self, pairs: list):
                                 pins1=s1,
                                 pins2=s2
                             )
-                            self.iconst.append(symmnet)
-                        logger.debug(f"adding symmetric net const: {symmnet}")
+                            # self.iconst.append(symmnet)
+                        # logger.debug(f"adding symmetric net const: {symmnet}")
                     else:
                         logger.debug(f"Skip symmetry: large fanout nets {key} {value} {pairs}")
                         # TODO Need update in placer to simplify this

align/gui/mockup.py

@@ -210,14 +210,15 @@ def make_tradeoff_fig_ha(df, log=False, scale='Blugrn', lambda_coeff=1.0):
         log_sweep_y = log_product - np.log(sweep_x)*lambda_coeff
         sweep_y = np.exp(log_sweep_y)
 
-        fig.add_trace(
+        if True:
+         fig.add_trace(
             go.Scatter(
                 x=sweep_x,
                 y=sweep_y,
                 mode='lines',
                 showlegend=False
             )
-        )
+         )
 
     define_colorscale( fig, df['constraint_penalty'])
     define_axes( fig, log, max_x, max_y, log_one_to_one=True)
@@ -363,7 +364,7 @@ def gen_dataframe( self):
         df['aspect_ratio'] = df['height'] / df['width']
 
         self.tagged_histos = {}
-        for atn, df_group0 in df.groupby(['abstract_template_name']):
+        for atn, df_group0 in df.groupby('abstract_template_name'):
             self.tagged_histos[atn] = defaultdict(list)
             for p, df_group1 in df_group0.groupby(list(self.axes)):
                 for row_index, row in df_group1.iterrows():

align/main.py

@@ -159,6 +159,7 @@ def schematic2layout(netlist_dir, pdk_dir, netlist_file=None, subckt=None, worki
 
         logger.info(f"Reading netlist: {netlist} subckt={subckt}, flat={flatten}")
 
+        shutil.rmtree(topology_dir, ignore_errors=True)
         topology_dir.mkdir(exist_ok=True)
         primitive_lib = generate_hierarchy(netlist, subckt, topology_dir, flatten, pdk_dir)
     else:
@@ -172,6 +173,7 @@ def schematic2layout(netlist_dir, pdk_dir, netlist_file=None, subckt=None, worki
     sub_steps = [step for step in steps_to_run if '3_pnr:' in step]
 
     if '2_primitives' in steps_to_run:
+        shutil.rmtree(primitive_dir, ignore_errors=True)
         primitive_dir.mkdir(exist_ok=True)
         primitives = generate_primitives(primitive_lib, pdk_dir, primitive_dir, netlist_dir)
         with (primitive_dir / '__primitives__.json').open('wt') as fp:

demo/ckt_bias_generator/ckt_bias_generator.const.json

@@ -0,0 +1,32 @@
+[
+  {"constraint": "ConfigureCompiler","auto_constraint": false,"propagate": true,"identify_array": false,"fix_source_drain": false,"merge_series_devices": false,"merge_parallel_devices": false,"remove_dummy_devices": false,"remove_dummy_hierarchies": false},
+  {"constraint": "PowerPorts","ports": ["vccd","vcca"]},
+  {"constraint": "GroundPorts","ports": ["vssx"]},
+  {"constraint": "DoNotRoute","nets": ["vssx","vccd","vcca"]},
+  {"constraint": "GroupBlocks","instances": ["nand0","nand1","inv09"],"instance_name": "xdig"},
+  {"constraint": "GroupBlocks","instances": ["R0","i12","i21","i13","i20","qn3"],"instance_name": "xoutp", "constraints": [
+    {"constraint": "ConfigureCompiler", "auto_constraint": false, "propagate": true},
+    {"constraint": "DoNotIdentify", "instances": ["i12", "i21", "i13", "i20", "qn3"]},
+    {"constraint": "Floorplan", "order": true, "regions": [["R0"], ["i12", "i21", "i13"], ["i20", "qn3"]]},
+    {"constraint": "Align", "line": "v_left", "instances": ["R0", "i12", "i20"]}
+  ]},
+  {"constraint": "GroupBlocks","instances": ["R6","i15","i35","i36","i22","i16"],"instance_name": "xoutn", "constraints": [
+    {"constraint": "ConfigureCompiler", "auto_constraint": false, "propagate": true},
+    {"constraint": "DoNotIdentify", "instances": ["i15", "i35", "i36", "i22", "i16"]},
+    {"constraint": "Floorplan", "order": true, "regions": [["i35", "i36"], ["i15", "i22", "i16"], ["R6"]]},
+    {"constraint": "Align", "line": "v_left", "instances": ["i35", "i15", "R6"]}
+  ]},
+  {"constraint": "GroupBlocks","instances": ["i25","i32"],"instance_name": "xbiasp", "constraints": [
+    {"constraint": "ConfigureCompiler", "auto_constraint": false, "propagate": true},
+    {"constraint": "Floorplan", "regions": [["i25"], ["i32"]]}
+  ]},
+  {"constraint": "GroupBlocks","instances": ["i24","i27"],"instance_name": "xbiasn", "constraints": [
+    {"constraint": "ConfigureCompiler", "auto_constraint": false, "propagate": true},
+    {"constraint": "Floorplan", "regions": [["i24"], ["i27"]]}
+  ]},
+  {"constraint": "Floorplan","order": true,"symmetrize": false,"regions": [
+    ["xbiasp","i0","xoutp"],
+    ["xdig"],
+    ["xbiasn","i14","xoutn"]]
+  }
+]

demo/ckt_bias_generator/ckt_bias_generator.const.json.0

@@ -0,0 +1,32 @@
+[
+  {"constraint": "ConfigureCompiler","auto_constraint": false,"propagate": true,"identify_array": false,"fix_source_drain": false,"merge_series_devices": false,"merge_parallel_devices": false,"remove_dummy_devices": false,"remove_dummy_hierarchies": false},
+  {"constraint": "PowerPorts","ports": ["vccd","vcca"]},
+  {"constraint": "GroundPorts","ports": ["vssx"]},
+  {"constraint": "DoNotRoute","nets": ["vssx","vccd","vcca"]},
+  {"constraint": "GroupBlocks","instances": ["nand0","nand1","inv09"],"instance_name": "xdig"},
+  {"constraint": "GroupBlocks","instances": ["R0","i12","i21","i13","i20","qn3"],"instance_name": "xoutp", "constraints": [
+    {"constraint": "ConfigureCompiler", "auto_constraint": false, "propagate": true},
+    {"constraint": "DoNotIdentify", "instances": ["i12", "i21", "i13", "i20", "qn3"]},
+    {"constraint": "Floorplan", "order": true, "regions": [["R0"], ["i12", "i21", "i13"], ["i20", "qn3"]]},
+    {"constraint": "Align", "line": "v_left", "instances": ["R0", "i12", "i20"]}
+  ]},
+  {"constraint": "GroupBlocks","instances": ["R6","i15","i35","i36","i22","i16"],"instance_name": "xoutn", "constraints": [
+    {"constraint": "ConfigureCompiler", "auto_constraint": false, "propagate": true},
+    {"constraint": "DoNotIdentify", "instances": ["i15", "i35", "i36", "i22", "i16"]},
+    {"constraint": "Floorplan", "order": true, "regions": [["i35", "i36"], ["i15", "i22", "i16"], ["R6"]]},
+    {"constraint": "Align", "line": "v_left", "instances": ["i35", "i15", "R6"]}
+  ]},
+  {"constraint": "GroupBlocks","instances": ["i25","i32"],"instance_name": "xbiasp", "constraints": [
+    {"constraint": "ConfigureCompiler", "auto_constraint": false, "propagate": true},
+    {"constraint": "Floorplan", "regions": [["i25"], ["i32"]]}
+  ]},
+  {"constraint": "GroupBlocks","instances": ["i24","i27"],"instance_name": "xbiasn", "constraints": [
+    {"constraint": "ConfigureCompiler", "auto_constraint": false, "propagate": true},
+    {"constraint": "Floorplan", "regions": [["i24"], ["i27"]]}
+  ]},
+  {"constraint": "Floorplan","order": true,"symmetrize": false,"regions": [
+    ["xbiasp","i0","xoutp"],
+    ["xdig"],
+    ["xbiasn","i14","xoutn"]]
+  }
+]

demo/ckt_bias_generator/ckt_bias_generator.sp

@@ -0,0 +1,82 @@
+.subckt dig22nand a b o1 vccd vssx
+.ends
+.subckt dig22inv a o1 vccd vssx
+.ends
+.subckt folded_cascode_n ina inb incsa incsl outb vcca vssx
+qn1 diffa ina incsa vssx npv drain=sig m=2 nf=6 source=sig nfin=4
+qn2 diffb inb incsa vssx npv drain=sig m=2 nf=6 source=sig nfin=4
+qp6<0> incsl incsl casp vcca ppv stack=2 drain=sig m=4 source=sig nfin=4
+qp6<1> incsl incsl casp vcca ppv stack=2 drain=sig m=4 source=sig nfin=4
+qp2 casn incsl diffa vcca ppv stack=2 drain=sig m=8 source=sig nfin=4
+qp5<0> casp casp vcca vcca ppv stack=2 drain=sig m=4 source=pwr nfin=4
+qp5<1> casp casp vcca vcca ppv stack=2 drain=sig m=4 source=pwr nfin=4
+qp4 diffa casp vcca vcca ppv stack=2 drain=sig m=8 source=pwr nfin=4
+qp1 outb incsl diffb vcca ppv stack=2 drain=sig m=8 source=sig nfin=4
+qp3 diffb casp vcca vcca ppv stack=2 drain=sig m=8 source=pwr nfin=4
+qn6 net1 casn vssx vssx npv stack=2 drain=sig m=8 source=gnd nfin=4
+qn3 outb casn net2 vssx npv stack=2 drain=sig m=8 source=sig nfin=4
+qn5 net2 casn vssx vssx npv stack=2 drain=sig m=8 source=gnd nfin=4
+qn4 casn casn net1 vssx npv stack=2 drain=sig m=8 source=sig nfin=4
+.ends
+.subckt folded_cascode_p ina inb incsa incsl outb vcca vssx
+qn2 diffb inb incsa vcca ppv drain=sig m=2 nf=6 source=sig nfin=4
+qn1 diffa ina incsa vcca ppv drain=sig m=2 nf=6 source=sig nfin=4
+qp4 net1 casp vcca vcca ppv stack=2 drain=sig m=8 source=pwr nfin=4
+qp2 casp casp net1 vcca ppv stack=2 drain=sig m=8 source=sig nfin=4
+qp1 outb casp net2 vcca ppv stack=2 drain=sig m=8 source=sig nfin=4
+qp3 net2 casp vcca vcca ppv stack=2 drain=sig m=8 source=pwr nfin=4
+qn5 diffb casn vssx vssx npv stack=2 drain=sig m=16 source=gnd nfin=4
+qn3 outb incsl diffb vssx npv stack=2 drain=sig m=8 source=sig nfin=4
+qp6<0> casn casn vssx vssx npv stack=2 drain=sig m=4 source=gnd nfin=4
+qp6<1> casn casn vssx vssx npv stack=2 drain=sig m=4 source=gnd nfin=4
+qp5<0> incsl incsl casn vssx npv stack=2 drain=sig m=4 source=sig nfin=4
+qp5<1> incsl incsl casn vssx npv stack=2 drain=sig m=4 source=sig nfin=4
+qn4 casp incsl diffa vssx npv stack=2 drain=sig m=8 source=sig nfin=4
+qn6 diffa casn vssx vssx npv stack=2 drain=sig m=16 source=gnd nfin=4
+.ends
+.subckt nbias_gen iout en vcca vssx
+i6 vssx net1 vssx vssx npv stack=4 drain=sig m=2 source=gnd nfin=4
+mn0 net1 net2 net15 vssx npv stack=4 drain=sig m=8 source=sig nfin=4
+qn1 net2 net2 vssx vssx npv stack=4 drain=sig m=2 source=gnd nfin=4
+qp1 net2 net1 vcca vcca ppv stack=4 drain=sig m=2 source=pwr nfin=4
+mp1 iout net1 vcca vcca ppv stack=4 drain=sig m=2 source=pwr nfin=4
+mp0 net1 net1 vcca vcca ppv stack=4 drain=sig m=2 source=pwr nfin=4
+i9 net15 en net5 vssx npv drain=sig m=1 nf=2 source=sig nfin=4
+i0 net1 vssx vssx vssx npv drain=sig m=1 nf=4 source=gnd nfin=4
+r0 net5 vssx tfr_prim w=1 l=1
+.ends
+.subckt pbias_gen iout en vcca vssx
+mn0 net4 net4 vssx vssx npv stack=4 drain=sig m=2 source=gnd nfin=4
+qn1 net3 net4 vssx vssx npv stack=4 drain=sig m=2 source=gnd nfin=4
+mn1 iout net4 vssx vssx npv stack=4 drain=sig m=2 source=gnd nfin=4
+qp1 net3 net3 vcca vcca ppv drain=sig m=2 nf=2 source=pwr nfin=4
+mp0 net4 net3 net16 vcca ppv drain=sig m=8 nf=2 source=sig nfin=4
+i9 net16 en net5 vcca ppv drain=sig m=1 nf=2 source=sig nfin=4
+i6 vcca net4 vcca vcca ppv drain=sig m=1 nf=2 source=pwr nfin=4
+i0 net4 vcca vcca vcca ppv drain=sig m=1 nf=4 source=pwr nfin=4
+r0 vcca net5 tfr_prim w=1 l=1
+.ends
+.subckt ckt_bias_generator v1n v1p v2n v2p ctrl n p vccd vcca vref_n vref_p vssx
+i20 v1p v1p vssx vssx npv stack=2 drain=sig m=1 source=gnd nfin=4
+qn3 v2p v2p vssx vssx npv stack=2 drain=sig m=1 source=gnd nfin=4
+i21 v1p gate_p vcca vcca ppv drain=sig m=1 nf=2 source=pwr nfin=4
+i12 fb_ota_n gate_p vcca vcca ppv drain=sig m=1 nf=2 source=pwr nfin=4
+i13 v2p gate_p vcca vcca ppv drain=sig m=1 nf=2 source=pwr nfin=4
+nand1 ctrl n net19 vccd vssx dig22nand
+nand0 p ctrl net6 vccd vssx dig22nand
+i0 fb_ota_n vref_n i_incsa_n i_incsl_n gate_p vcca vssx folded_cascode_n
+i15 fb_ota_p gate_n vssx vssx npv drain=sig m=1 nf=2 source=gnd nfin=4
+i16 v2n gate_n vssx vssx npv drain=sig m=1 nf=2 source=gnd nfin=4
+i22 v1n gate_n vssx vssx npv drain=sig m=1 nf=2 source=gnd nfin=4
+i14 fb_ota_p vref_p i_incsa_p i_incsl_p gate_n vcca vssx folded_cascode_p
+i35 v1n v1n vcca vcca ppv stack=2 drain=sig m=1 source=pwr nfin=4
+i36 v2n v2n vcca vcca ppv stack=2 drain=sig m=1 source=pwr nfin=4
+r6 vcca fb_ota_p tfr_prim w=1 l=1
+r0 fb_ota_n vssx tfr_prim w=1 l=1
+inv09 net19 net21 vccd vssx dig22inv
+i24 i_incsa_p net21 vcca vssx nbias_gen
+i27 i_incsl_p net21 vcca vssx nbias_gen
+i25 i_incsa_n net6 vcca vssx pbias_gen
+i32 i_incsl_n net6 vcca vssx pbias_gen
+.ends ckt_bias_generator
+.END

demo/ckt_bias_generator/folded_cascode_n.const.json

@@ -0,0 +1,20 @@
+[
+  {"constraint": "ConfigureCompiler","auto_constraint": false,"propagate": true,"identify_array": false,"fix_source_drain": false,"merge_series_devices": false,"merge_parallel_devices": false,"remove_dummy_devices": false,"remove_dummy_hierarchies": false},
+  {"constraint": "PowerPorts","ports": ["vcca"]},
+  {"constraint": "GroundPorts","ports": ["vssx"]},
+  {"constraint": "DoNotRoute","nets": ["vssx","vcca"]},
+  {"constraint": "GroupBlocks","instances": ["qp4","qp3"],"instance_name": "xqp43","generator": {"name": "MOS","parameters": {"legal_sizes": [{"y": 2}]}}},
+  {"constraint": "GroupBlocks","instances": ["qp2","qp1"],"instance_name": "xqp21","generator": {"name": "MOS","parameters": {"legal_sizes": [{"y": 2}]}}},
+  {"constraint": "GroupBlocks","instances": ["qn4","qn3"],"instance_name": "xqn43","generator": {"name": "MOS","parameters": {"legal_sizes": [{"y": 2}]}}},
+  {"constraint": "GroupBlocks","instances": ["qn6","qn5"],"instance_name": "xqn56","generator": {"name": "MOS","parameters": {"legal_sizes": [{"y": 2}]}}},
+  {"constraint": "GroupBlocks","instances": ["qn1","qn2"],"instance_name": "xqn12","generator": {"name": "MOS","parameters": {"legal_sizes": [{"y": 2}]}}},
+  {"constraint": "SameTemplate","instances": ["qp5<0>","qp5<1>"]},
+  {"constraint": "SameTemplate","instances": ["qp6<0>","qp6<1>"]},
+  {"constraint": "Floorplan","order": true,"symmetrize": true,"regions": [
+    ["xqn56"],
+    ["xqn43"],
+    ["qp6<0>", "xqp21", "qp6<1>"],
+    ["qp5<0>", "xqp43", "qp5<1>"],
+    ["xqn12"]]
+  }
+]

demo/ckt_bias_generator/folded_cascode_p.const.json

@@ -0,0 +1,19 @@
+[
+  {"constraint": "ConfigureCompiler","auto_constraint": false,"propagate": true,"identify_array": false,"fix_source_drain": false,"merge_series_devices": false,"merge_parallel_devices": false,"remove_dummy_devices": false,"remove_dummy_hierarchies": false},
+  {"constraint": "PowerPorts","ports": ["vcca"]},
+  {"constraint": "GroundPorts","ports": ["vssx"]},
+  {"constraint": "DoNotRoute","nets": ["vssx","vcca"]},
+  {"constraint": "GroupBlocks","instances": ["qp4","qp3"],"instance_name": "xqp43","generator": {"name": "MOS","parameters": {"legal_sizes": [{"y": 2}]}}},
+  {"constraint": "GroupBlocks","instances": ["qp2","qp1"],"instance_name": "xqp21","generator": {"name": "MOS","parameters": {"legal_sizes": [{"y": 2}]}}},
+  {"constraint": "GroupBlocks","instances": ["qn4","qn3"],"instance_name": "xqn43","generator": {"name": "MOS","parameters": {"legal_sizes": [{"y": 2}]}}},
+  {"constraint": "GroupBlocks","instances": ["qn6","qn5"],"instance_name": "xqn65","generator": {"name": "MOS","parameters": {"legal_sizes": [{"y": 4}]}}},
+  {"constraint": "GroupBlocks","instances": ["qn1","qn2"],"instance_name": "xqn12","generator": {"name": "MOS","parameters": {"legal_sizes": [{"y": 2}]}}},
+  {"constraint": "SameTemplate","instances": ["qp5<0>","qp5<1>"]},
+  {"constraint": "SameTemplate","instances": ["qp6<0>","qp6<1>"]},
+  {"constraint": "Floorplan","order": true,"symmetrize": true,"regions": [
+    ["xqn12"],
+    ["qp6<0>","xqn65","qp6<1>"],
+    ["qp5<0>","xqn43","qp5<1>"],
+    ["xqp21"],
+    ["xqp43"]]}
+]

demo/ckt_bias_generator/nbias_gen.const.json

@@ -0,0 +1,18 @@
+[
+  {"constraint": "ConfigureCompiler","auto_constraint": false,"propagate": true,"identify_array": false,"fix_source_drain": false,"merge_series_devices": false,"merge_parallel_devices": false,"remove_dummy_devices": false,"remove_dummy_hierarchies": false},
+  {"constraint": "PowerPorts","ports": ["vcca"]},
+  {"constraint": "GroundPorts","ports": ["vssx"]},
+  {"constraint": "DoNotRoute","nets": ["vssx","vcca"]},
+  {"constraint": "GroupBlocks","instances": ["mp0"],"instance_name": "xmp0","generator": {"name": "MOS","parameters": {"legal_sizes": [{"y": 2}]}}},
+  {"constraint": "GroupBlocks","instances": ["qp1"],"instance_name": "xqp1","generator": {"name": "MOS","parameters": {"legal_sizes": [{"y": 2}]}}},
+  {"constraint": "GroupBlocks","instances": ["mp1"],"instance_name": "xmp1","generator": {"name": "MOS","parameters": {"legal_sizes": [{"y": 2}]}}},
+  {"constraint": "GroupBlocks","instances": ["mn0"],"instance_name": "xmn0","generator": {"name": "MOS","parameters": {"legal_sizes": [{"y": 2}]}}},
+  {"constraint": "GroupBlocks","instances": ["qn1"],"instance_name": "xqn1","generator": {"name": "MOS","parameters": {"legal_sizes": [{"y": 2}]}}},
+  {"constraint": "Floorplan","order": true,"symmetrize": false,"regions": [
+    ["i0","i6"],
+    ["xmp0","xqp1","xmp1"],
+    ["xmn0","xqn1"],
+    ["i9"]]},
+  {"constraint": "Order","direction": "left_to_right","instances": ["r0","i0"]},
+  {"constraint": "Order","direction": "left_to_right","instances": ["r0","i9"]}
+]

demo/ckt_bias_generator/pbias_gen.const.json

@@ -0,0 +1,18 @@
+[
+  {"constraint": "ConfigureCompiler","auto_constraint": false,"propagate": true,"identify_array": false,"fix_source_drain": false,"merge_series_devices": false,"merge_parallel_devices": false,"remove_dummy_devices": false,"remove_dummy_hierarchies": false},
+  {"constraint": "PowerPorts","ports": ["vcca"]},
+  {"constraint": "GroundPorts","ports": ["vssx"]},
+  {"constraint": "DoNotRoute","nets": ["vssx","vcca"]},
+  {"constraint": "GroupBlocks","instances": ["mp0"],"instance_name": "xmp0","generator": {"name": "MOS","parameters": {"legal_sizes": [{"y": 2}]}}},
+  {"constraint": "GroupBlocks","instances": ["qp1"],"instance_name": "xqp1","generator": {"name": "MOS","parameters": {"legal_sizes": [{"y": 2}]}}},
+  {"constraint": "GroupBlocks","instances": ["mn0"],"instance_name": "xmn0","generator": {"name": "MOS","parameters": {"legal_sizes": [{"y": 2}]}}},
+  {"constraint": "GroupBlocks","instances": ["qn1"],"instance_name": "xqn1","generator": {"name": "MOS","parameters": {"legal_sizes": [{"y": 2}]}}},
+  {"constraint": "GroupBlocks","instances": ["mn1"],"instance_name": "xmn1","generator": {"name": "MOS","parameters": {"legal_sizes": [{"y": 2}]}}},
+  {"constraint": "Floorplan","order": true,"symmetrize": false,"regions": [
+    ["i0","i6"],
+    ["xmn0","xqn1","xmn1"],
+    ["xmp0","xqp1"],
+    ["i9"]]},
+  {"constraint": "Order","direction": "left_to_right","instances": ["r0","i0"]},
+  {"constraint": "Order","direction": "left_to_right","instances": ["r0","i9"]}
+]

demo/ckt_comparator/ckt_comparator.const.json

@@ -0,0 +1,4 @@
+[
+  {"constraint": "PowerPorts", "ports": ["vccx"]},
+  {"constraint": "GroundPorts", "ports": ["vssx"]}
+]

demo/ckt_comparator/ckt_comparator.const.json.0

@@ -0,0 +1,4 @@
+[
+  {"constraint": "PowerPorts", "ports": ["vccx"]},
+  {"constraint": "GroundPorts", "ports": ["vssx"]}
+]