GitHub - ArasValizadeh/MIPS-Pipeline: My Final Project in the Computer Architecture course involved implementing the MIPS architecture using Verilog. This project required designing and simulating the MIPS processor, including key components such as the ALU, control unit, registers, and memory. The implementation focused on executing basic MIPS instructions, managing data flow.

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My Final Project in the Computer Architecture course involved implementing the MIPS architecture using Verilog. This project required designing and simulating the MIPS processor, including key components such as the ALU, control unit, registers, and memory. The implementation focused on executing basic MIPS instructions, managing data flow.

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Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
ALU.v		ALU.v
ALUControl.v		ALUControl.v
Adder.v		Adder.v
Comparator.v		Comparator.v
ControlUnit.v		ControlUnit.v
DataMemory.v		DataMemory.v
DataMemory2.v		DataMemory2.v
EX_Mem_Reg.v		EX_Mem_Reg.v
Forwarding.v		Forwarding.v
Hazard.v		Hazard.v
ID_EX_Reg.v		ID_EX_Reg.v
IF_ID_Reg.v		IF_ID_Reg.v
InstructionMemory.v		InstructionMemory.v
InstructionMemory2.v		InstructionMemory2.v
Mem1_Mem2_Reg.v		Mem1_Mem2_Reg.v
Mem_Wb_Reg.v		Mem_Wb_Reg.v
Mux2x110Bits.v		Mux2x110Bits.v
Mux2x132Bits.v		Mux2x132Bits.v
Mux2x15Bits.v		Mux2x15Bits.v
Mux3x132Bits.v		Mux3x132Bits.v
PC.v		PC.v
ProjectReport-ArasValizadeh.docx		ProjectReport-ArasValizadeh.docx
ProjectReport-ArasValizadeh.pdf		ProjectReport-ArasValizadeh.pdf
RegisterFile.v		RegisterFile.v
ShiftLeft.v		ShiftLeft.v
SignExtend.v		SignExtend.v
TestBench.v		TestBench.v
TestBench2.v		TestBench2.v