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Current State ------------- 1) Works with only the latest versions of LLVM (11 and above) 2) the instructions so far implemented: ADC, ADD, LDI Design Issues ------------- A unique feature of AVR is that it maps registers directly to RAM, thus we theoretically can't represent registers as variables, but instead shall model them as memory addresses[^1]. Treating this AVR feature fairly, will render quite hard to read and to analyze code. After digging through the forums, datasheets, compilers source code, and grepping avr-objdump outputs, we can presume that C compilers are not leveraging this feature and use normal reads and writes to access registers, instead of loads and stores. And the memory-mapping of registers is mostly reserved RAM-less AVR boards, where 32 register plays the role of minimal RAM. Of course, it doesn't mean that the malicious code can't exploit this. With this in mind, we still decided to model AVR as normal register-based machine but add a command-line option later, that will enable a conservative model, that lacks registers. Formally, our current lifter implementation (the one with registers) just assumes that all addresses in load and stores operation are greater than 32. [^1]: And yes, `*0 = 'B'` is a perfectly valid code on AVR that writes `0x42` into the `R0` register.
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Current State
Since LLVM is not yet ready for AVR we switched to Ghidra. We still have to use LLVM as a loader (and it proves to fail on AVR as well, but we addressed it). The lifter and decode work well so far, but we lack good testing binaries to be sure about that. The data model of the lifter (namely the registers) is not yet clear.
We will try adding some tests before merging.