AIST-TSN is an open source project developed by the National Institute of Advanced Industrial Science and Technology (AIST), Japan. It focuses on enabling hardware design support for Time-Sensitive Networking (TSN) technology. TSN is a set of IEEE standards that extends Ethernet to support real-time, deterministic communication — essential for applications in industrial automation, automotive systems, and cyber-physical infrastructure. This repository provides design assets, reference implementations, verification tools, and evaluation experiments for TSN features targeting FPGA or ASIC-based hardware development. The project aims to accelerate TSN adoption by offering reusable, standards-aligned components and resources for developers, researchers, and system integrators. We aim to provide an open platform that can be used as a reference design so scientists can implement their desired functionalities and make the different evaluations and comparisons to highlight the appropriate design choices for a given TSN system.
This repository provides the hardware design of a reconfigurable FPGA-based Layer-2 network switch supporting Time-Sensitive Networking (TSN). The switch supports two different scheduling algorithms, which have been implemented and validated on an AMD Xilinx KC705 FPGA evaluation board and a Digilent ZedBoard FPGA development board. To the best of our knowledge, this is the first open-source implementation of a Credit-Based Shaping (CBS) switch and the first real-world implementation of an Asynchronous Traffic Shaping (ATS) switch.
Supported switch configurations:
- Layer-2 switch supporting Credit-Based Shaping (CBS)
- Layer-2 switch supporting Asynchronous Traffic Shaping (ATS)
This repository provides Ethernet Frame Crafter & Capture (EFCC), a flexible FPGA-based frame generation and capture measurement tool for TSN research and developement. EFCC is capable of generating multiple TSN flows with different characteristics, where the frame size, frame rate, and burst size are independently set for each flow. In addition, it can record the arrival times of all the frames with a high-precision hardware clock without any loss of the arrival time records, even with the shortest frame size. EFFC is implemented and validated on an AMD Xilinx KC705 FPGA evaluation board.
This repository provides an implementation of a Time-Sensitive Networking (TSN) endpoint for Asynchronous Traffic Shaping (ATS). It supports network interface cards with transmit timing control, such as Intel i210 and i225 NICs. The implementation generates IEEE-compliant ATS flows based on the Committed Information Rate and Committed Burst Size. To the best of our knowledge, this is the first real-world implementation of an ATS endpoint.
When using the provided designs in this repository, please refer to the following citations:
AIST TSN Switch for Credit-based Shaping (CBS):
Akram BEN AHMED, Takahiro HIROFUCHI, and Takaaki FUKAI "FPGA-based Network Switch Architecture Supporting Credit Based Shaper for Time Sensitive Networks", The 29th IEEE International Conference on Emerging Technologies and Factory Automation (ETFA2024), pp. 1-8, Sep 2024, doi: 10.1109/ETFA61755.2024.10710853, https://ieeexplore.ieee.org/document/10710853
AIST TSN Switch for Asynchronous Traffic Shaping (ATS):
Akram BEN AHMED, Takahiro HIROFUCHI, and Takaaki FUKAI, "Hardware design and Evaluation of an FPGA-based Network Switch Supporting Asynchronous Traffic Shaping for Time Sensitive Networking", IEEE Access, vol. 12, pp. 123149-123165, Aug 2024, doi: 10.1109/ACCESS.2024.3451448, https://ieeexplore.ieee.org/document/10658978
AIST Ethernet Frame Crafter & Capture (EFCC):
Akram BEN AHMED, Takahiro HIROFUCHI, and Takaaki FUKAI, "EFCC: Ethernet Frame Crafter & Capture for TSN Research", The 50th IEEE Conference on Local Computer Networks (LCN2025), pp. 1-9, October 2025, doi: 10.1109/LCN65610.2025.11146312, https://ieeexplore.ieee.org/document/11146312
Best Paper Award Candidate🏆
AIST TSN Endpoint Supporting Asynchronous Traffic Shaping (ATS)
Takahiro HIROFUCHI, Akram BEN AHMED, and Takaaki FUKAI, "Implementation and Evaluation of a Time-Sensitive Networking Endpoint for Asynchronous Traffic Shaping", IEEE Access, Early Access, 2026, doi: 10.1109/ACCESS.2026.3661078, https://ieeexplore.ieee.org/document/11372664
The Continuum Computing Architecture Research Group (CCARG), the Intelligent Platforms Research Institute, the National Institute of Advanced Industrial Science and Technology (AIST), Japan.
E-mail: M-digiarc-ccirt-contact-ml@aist.go.jp
We are hiring postdocs and technical staffs. Collaborations are also welcome.
This program is based on results obtained from the project, "Research and Development Project of the Enhanced infrastructures for Post 5G Information and Communication Systems" (JPNP20017), commissioned by the New Energy and Industrial Technology Development Organization (NEDO).
Copyright (c) 2024-2026 National Institute of Advanced Industrial Science and Technology (AIST) All rights reserved.
This software is released under the MIT License.