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Replace separate memory modules with single unified memory module DevContainer CI #45: Pull request #22 synchronize by spr4bhu
3m 12s spr4bhu:unified_mem
spr4bhu:unified_mem
3m 12s
Copilot code review Copilot code review #6: by Copilot AI
44s refs/pull/22/head
refs/pull/22/head
44s
Replace separate memory modules with single unified memory module DevContainer CI #44: Pull request #22 synchronize by spr4bhu
2m 46s spr4bhu:unified_mem
spr4bhu:unified_mem
2m 46s
Replace separate memory modules with single unified memory module DevContainer CI #43: Pull request #22 synchronize by spr4bhu
2m 37s spr4bhu:unified_mem
spr4bhu:unified_mem
2m 37s
Replace separate memory modules with single unified memory module DevContainer CI #42: Pull request #22 opened by spr4bhu
2m 33s spr4bhu:unified_mem
spr4bhu:unified_mem
2m 33s
[BUGFIX] SLT/SLTU/SLTI/SLTIU now return 1 or 0 instead of 0xFFFFFFFF DevContainer CI #41: Commit 37d3aab pushed by 5iri
2m 37s main
main
2m 37s
Fix ALU SLT/SLTU comparison bug and register file improvements DevContainer CI #40: Pull request #19 synchronize by 5iri
2m 44s spr4bhu:SLT_BUG
spr4bhu:SLT_BUG
2m 44s
[CI] fix CI; use Verilator for sim; and add contest.py for config DevContainer CI #39: Commit c6d46e5 pushed by 5iri
2m 46s main
main
2m 46s
ci fix DevContainer CI #37: Pull request #20 synchronize by 5iri
2m 52s 5iri:fixci
5iri:fixci
2m 52s
ci fix DevContainer CI #36: Pull request #20 synchronize by 5iri
1h 3m 44s 5iri:fixci
5iri:fixci
1h 3m 44s
ci fix DevContainer CI #35: Pull request #20 synchronize by 5iri
1m 8s 5iri:fixci
5iri:fixci
1m 8s
ci fix DevContainer CI #34: Pull request #20 synchronize by 5iri
59s 5iri:fixci
5iri:fixci
59s
ci fix DevContainer CI #33: Pull request #20 opened by 5iri
49s 5iri:fixci
5iri:fixci
49s
Copilot code review Copilot code review #5: by Copilot AI
3m 5s refs/pull/20/head
refs/pull/20/head
3m 5s
Add Formal Verification Flow Using Yosys's riscv-formal DevContainer CI #32: Pull request #16 synchronize by 5iri
19s 5iri:func_verif
5iri:func_verif
19s
Fix ALU SLT/SLTU comparison bug and register file improvements DevContainer CI #31: Pull request #19 synchronize by spr4bhu
22s spr4bhu:SLT_BUG
spr4bhu:SLT_BUG
22s
Fix ALU SLT/SLTU comparison bug and register file improvements DevContainer CI #30: Pull request #19 opened by spr4bhu
Action required spr4bhu:SLT_BUG
spr4bhu:SLT_BUG
Action required
Add Formal Verification Flow Using Yosys's riscv-formal DevContainer CI #29: Pull request #16 synchronize by 5iri
22s 5iri:func_verif
5iri:func_verif
22s
Copilot code review Copilot code review #4: by Copilot AI
2m 21s refs/pull/16/head
refs/pull/16/head
2m 21s
Add instruction cache and store-load forwarding DevContainer CI #28: Pull request #18 synchronize by spr4bhu
Action required spr4bhu:icache
spr4bhu:icache
Action required
Add instruction cache and store-load forwarding DevContainer CI #27: Pull request #18 synchronize by spr4bhu
Action required spr4bhu:icache
spr4bhu:icache
Action required
Add instruction cache and store-load forwarding DevContainer CI #26: Pull request #18 synchronize by spr4bhu
Action required spr4bhu:icache
spr4bhu:icache
Action required
Add instruction cache and store-load forwarding DevContainer CI #25: Pull request #18 synchronize by spr4bhu
Action required spr4bhu:icache
spr4bhu:icache
Action required
Add instruction cache and store-load forwarding DevContainer CI #21: Pull request #18 synchronize by spr4bhu
18s spr4bhu:icache
spr4bhu:icache
18s
Add Formal Verification Flow Using Yosys's riscv-formal DevContainer CI #19: Pull request #16 synchronize by 5iri
19s 5iri:func_verif
5iri:func_verif
19s