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Small error on the design. updated version with the corrections
Final report
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This fabrication run is closed. Please submit your design in the next fabrication run. https://github.com/SiEPIC/openEBL-2026-02 |
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final report form mRamalho |
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This is an experimental feature. The goal is to run a circuit simulation on the design, and return the results for human verification. ✅ Simulation results for stdout: To re-run this simulation, please make a change to the layout file (simply running V verification will change the date stamp in the layout), save it, and upload it to your GitHub fork. This will trigger this simulation to run again. I hereby grant you permission to use these plots for inclusion in a course report. |
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