Revert "Revert "dbritch oas file""

[MateoBCalles]

Reverts #374

[lukasc-ubc]

This is an experimental feature. The goal is to run a circuit simulation on the design, and return the results for human verification.

✅ Simulation results for EBeam_edxdbritch.oas

stdout:

KLayout SiEPIC-Tools version 0.5.29
New version of SiEPIC-Tools is available (0.5.31 vs 0.5.29).
Version check, time: 0.21161985397338867 seconds
SiEPIC-EBeam-PDK Python module: siepic_ebeam_pdk, KLayout technology: EBeam
SiEPIC-EBeam-PDK Python module: pymacros, v0.4.50
Libraries associated with Technology EBeam: ['EBeam', 'EBeam-ANT', 'EBeam-Dream', 'EBeam-SiN', 'EBeam_Beta']
PDK folder: /home/lukasc/.local/lib/python3.10/site-packages/siepic_ebeam_pdk/__init__.py

Found 14 opt-in labels: ['opt_in_TE_1550_device_dbritch_bragg2', 'opt_in_TE_1550_device_dbritch_bragg4', 'opt_in_TE_1550_device_dbritch_mzi1', 'opt_in_TE_1550_device_dbritch_bragg6', 'opt_in_TE_1550_device_dbritch_bragg10', 'opt_in_TE_1550_device_dbritch_control', 'opt_in_TE_1550_device_dbritch_bragg7', 'opt_in_TE_1550_device_dbritch_bragg8', 'opt_in_TE_1550_device_dbritch_bragg9', 'opt_in_TE_1550_device_dbritch_bragg3', 'opt_in_TE_1550_device_dbritch_mzi3', 'opt_in_TE_1550_device_dbritch_bragg1', 'opt_in_TE_1550_device_dbritch_bragg5', 'opt_in_TE_1550_device_dbritch_mzi2']

Running simulation for opt_in_TE_1550_device_dbritch_bragg2
Design for Test rules from PDK: /home/lukasc/.local/lib/python3.10/site-packages/siepic_ebeam_pdk/DFT.xml
No simulation results available for input 2 for opt_in_TE_1550_device_dbritch_bragg2
Simulation completed for opt_in_TE_1550_device_dbritch_bragg2.

Running simulation for opt_in_TE_1550_device_dbritch_bragg4
Design for Test rules from PDK: /home/lukasc/.local/lib/python3.10/site-packages/siepic_ebeam_pdk/DFT.xml
No simulation results available for input 2 for opt_in_TE_1550_device_dbritch_bragg4
Simulation completed for opt_in_TE_1550_device_dbritch_bragg4.

Running simulation for opt_in_TE_1550_device_dbritch_mzi1
Design for Test rules from PDK: /home/lukasc/.local/lib/python3.10/site-packages/siepic_ebeam_pdk/DFT.xml
No simulation results available for input 2 for opt_in_TE_1550_device_dbritch_mzi1
Simulation completed for opt_in_TE_1550_device_dbritch_mzi1.

Running simulation for opt_in_TE_1550_device_dbritch_bragg6
Design for Test rules from PDK: /home/lukasc/.local/lib/python3.10/site-packages/siepic_ebeam_pdk/DFT.xml
No simulation results available for input 1 for opt_in_TE_1550_device_dbritch_bragg6
Simulation completed for opt_in_TE_1550_device_dbritch_bragg6.

Running simulation for opt_in_TE_1550_device_dbritch_bragg10
Design for Test rules from PDK: /home/lukasc/.local/lib/python3.10/site-packages/siepic_ebeam_pdk/DFT.xml
No simulation results available for input 1 for opt_in_TE_1550_device_dbritch_bragg10
Simulation completed for opt_in_TE_1550_device_dbritch_bragg10.

Running simulation for opt_in_TE_1550_device_dbritch_control
Design for Test rules from PDK: /home/lukasc/.local/lib/python3.10/site-packages/siepic_ebeam_pdk/DFT.xml
No simulation results available for input 1 for opt_in_TE_1550_device_dbritch_control
Simulation completed for opt_in_TE_1550_device_dbritch_control.

Running simulation for opt_in_TE_1550_device_dbritch_bragg7
Design for Test rules from PDK: /home/lukasc/.local/lib/python3.10/site-packages/siepic_ebeam_pdk/DFT.xml
No simulation results available for input 1 for opt_in_TE_1550_device_dbritch_bragg7
Simulation completed for opt_in_TE_1550_device_dbritch_bragg7.

Running simulation for opt_in_TE_1550_device_dbritch_bragg8
Design for Test rules from PDK: /home/lukasc/.local/lib/python3.10/site-packages/siepic_ebeam_pdk/DFT.xml
No simulation results available for input 1 for opt_in_TE_1550_device_dbritch_bragg8
Simulation completed for opt_in_TE_1550_device_dbritch_bragg8.

Running simulation for opt_in_TE_1550_device_dbritch_bragg9
Design for Test rules from PDK: /home/lukasc/.local/lib/python3.10/site-packages/siepic_ebeam_pdk/DFT.xml
No simulation results available for input 1 for opt_in_TE_1550_device_dbritch_bragg9
Simulation completed for opt_in_TE_1550_device_dbritch_bragg9.

Running simulation for opt_in_TE_1550_device_dbritch_bragg3
Design for Test rules from PDK: /home/lukasc/.local/lib/python3.10/site-packages/siepic_ebeam_pdk/DFT.xml
No simulation results available for input 2 for opt_in_TE_1550_device_dbritch_bragg3
Simulation completed for opt_in_TE_1550_device_dbritch_bragg3.

Running simulation for opt_in_TE_1550_device_dbritch_mzi3
Design for Test rules from PDK: /home/lukasc/.local/lib/python3.10/site-packages/siepic_ebeam_pdk/DFT.xml
No simulation results available for input 2 for opt_in_TE_1550_device_dbritch_mzi3
Simulation completed for opt_in_TE_1550_device_dbritch_mzi3.

Running simulation for opt_in_TE_1550_device_dbritch_bragg1
Design for Test rules from PDK: /home/lukasc/.local/lib/python3.10/site-packages/siepic_ebeam_pdk/DFT.xml
No simulation results available for input 2 for opt_in_TE_1550_device_dbritch_bragg1
Simulation completed for opt_in_TE_1550_device_dbritch_bragg1.

Running simulation for opt_in_TE_1550_device_dbritch_bragg5
Design for Test rules from PDK: /home/lukasc/.local/lib/python3.10/site-packages/siepic_ebeam_pdk/DFT.xml
No simulation results available for input 2 for opt_in_TE_1550_device_dbritch_bragg5
Simulation completed for opt_in_TE_1550_device_dbritch_bragg5.

Running simulation for opt_in_TE_1550_device_dbritch_mzi2
Design for Test rules from PDK: /home/lukasc/.local/lib/python3.10/site-packages/siepic_ebeam_pdk/DFT.xml
No simulation results available for input 1 for opt_in_TE_1550_device_dbritch_mzi2
Simulation completed for opt_in_TE_1550_device_dbritch_mzi2.
done in 0:01:45.4

📸 Simulation result image(s):

To re-run this simulation, please make a change to the layout file (simply running V verification will change the date stamp in the layout), save it, and upload it to your GitHub fork. This will trigger this simulation to run again.

I hereby grant you permission to use these plots for inclusion in a course report.

[github-actions]

Welcome, new contributor!

Thank you for uploading your design.

If you have not already checked it, please run the SiEPIC Functional Verification in KLayout, using the menu SiEPIC-Verification-Functional Layout Check (V).

We are using GitHub Actions to perform several automated checks. Please ensure that there are no failing checks. Each time you update the files in your fork, this pull request will trigger the automated verification. Check back in a few minutes once they are complete. Click on any failing check indiciated with a red "X" to see the detailed errors.

You may continue making updates to your design, or even contributing additonal designs (using a separate file name), until the tape-out deadline.