Twenty-One-Pilots

Welcome to the Twenty-One-Pilots repository! This repo contains 21 SystemVerilog modules for contributors to design, verify, and test as part of the Hacknight 7.0 challenge. Each module has its own folder with instructions and starter code.

Maintainer : Pranav M

Important

Add your rtl.sv and tb.sv into the module folder you want to design.

2to1_mux/
├─ rtl.sv       <- Your module implementation
├─ tb.sv        <- Testbench
└─ waveform.png <- Screenshot showing module works

Check out CONTRIBUTING.md for details regarding how to contribute to each module.

Available Modules

1. 2to1 Multiplexer
2. APB Master
3. APB Slave
4. APB System
5. Binary to Grey
6. Binary to One-hot
7. D Flip-Flop
8. Edge Detector
9. Fixed Priority Arbiter
10. LFSR
11. Muxes
12. Odd Counter
13. Parallel to Serial
14. Round Robin Arbiter
15. Second Bit Set from LSB
16. Self Reloading Counter
17. Sequence Detector
18. Shift Register
19. Simple ALU
20. Simple Memory Interface
21. Synchronous FIFO