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projects:ad9081_fmca_ebz_x_band: Fix synchronization#1823

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PopPaul2021 merged 4 commits intomainfrom
stingray_cw_fix
Feb 11, 2026
Merged

projects:ad9081_fmca_ebz_x_band: Fix synchronization#1823
PopPaul2021 merged 4 commits intomainfrom
stingray_cw_fix

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@PopPaul2021
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PR Description

The CDC was moved from the DO to the DMA.
The DMA clock was moved from the 250MHz PS clock to a 330MHz clock generated by the clock wizard.
The cache coherency was disabled in order to have the HP ports working at maximum frequency.

PR Type

  • Bug fix (change that fixes an issue)
  • New feature (change that adds new functionality)
  • Breaking change (has dependencies in other repos or will cause CI to fail)
  • Documentation

PR Checklist

  • I have followed the code style guidelines
  • I have performed a self-review of changes
  • I have compiled all hdl projects and libraries affected by this PR
  • I have tested in hardware affected projects, at least on relevant boards
  • I have commented my code, at least hard-to-understand parts
  • I have signed off all commits from this PR
  • I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
  • I have not introduced new Warnings/Critical Warnings on compilation
  • I have added new hdl testbenches or updated existing ones

@PopPaul2021
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Rebased the branch to the latest main and opened a PR on the Linux repository to match the HDL changes: analogdevicesinc/linux#3047

When the data offload source and destination clock are connected to the
same source there is a DRC error. By exposing the ASYNC_CLK parameter
and setting it to 0 in this use-case the issue is solved.

Signed-off-by: PopPaul2021 <paul.pop@analog.com>
Signed-off-by: PopPaul2021 <paul.pop@analog.com>
The CDC was moved from the DO to the DMA.
The DMA clock was moved from the 250MHz PS clock to a 330MHz clock
generated by the clock wizard.
The cache coherency was disabled in order to have the HP ports working at
maximum frequency.

Signed-off-by: PopPaul2021 <paul.pop@analog.com>
The block diagram of the HDL design was updated.
Notes regarding the system's use-case were added.

Signed-off-by: PopPaul2021 <paul.pop@analog.com>
@PopPaul2021
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RetriggerCI

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@PopPaul2021
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RetriggerCI

@sarpadi
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sarpadi commented Jan 26, 2026

RetriggerCI

@bia1708
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bia1708 commented Feb 6, 2026

RetriggerCI

@PopPaul2021 PopPaul2021 merged commit 9e3a005 into main Feb 11, 2026
7 of 8 checks passed
@PopPaul2021 PopPaul2021 deleted the stingray_cw_fix branch February 11, 2026 09:04
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4 participants