Reed-Solmon-Decoding

GF(16) Polynomial Evaluation with Pipelining

This repository contains a Verilog implementation of a GF(16) polynomial evaluator, designed with a pipelined architecture for efficient processing. It utilizes Block RAMs (BRAMs) for GF(16) multiplication and addition (XOR) operations, optimized for systems with a 2-clock cycle read latency.

Overview

The gf16_poly_eval_pipelined module evaluates a GF(16) polynomial of degree 14 using Horner's method. The pipelined design ensures high throughput by allowing parallel processing of polynomial terms.

Key Features

• GF(16) Polynomial Evaluation: Evaluates polynomials with coefficients and variables in GF(16).
• Pipelined Architecture: Optimizes performance by processing multiple polynomial terms concurrently.
• BRAM Utilization: Employs Block RAMs for GF(16) multiplication and addition, accommodating a 2-clock cycle read latency.

Modules

• gf16_poly_eval_pipelined.v: Top-level module for GF(16) polynomial evaluation.
• banana.v: A module that performs GF(16) multiplication and addition using BRAMs.
• tb_gf16_poly_eval_pipelined.v: Testbench for verifying the functionality of the gf16_poly_eval_pipelined module.
• blk_mem_gen_0 & blk_mem_gen_1: These are Xilinx IP cores for the BRAMs (GF XOR and GF MUL respectively). These need to be generated in Vivado.

Module Details

gf16_poly_eval_pipelined

This module is the top-level design for evaluating the GF(16) polynomial. It takes the input x and coefficients C1 and outputs the evaluated result.

Ports

• clk: Clock input.
• rst: Reset input.
• x: 4-bit input representing the GF(16) element to evaluate the polynomial at.
• C1: 60-bit input representing the coefficients of the polynomial (C14..C0).
• result: 4-bit output representing the result of the polynomial evaluation.

banana

This module performs the core GF(16) multiplication and addition operations using BRAMs.

Ports

• clk: Clock input.
• rst: Reset input.
• i: 4-bit input.
• q: 4-bit input.
• x: 4-bit input representing the GF(16) element to evaluate the polynomial at.
• out: 4-bit output.

tb_gf16_poly_eval_pipelined

This testbench verifies the gf16_poly_eval_pipelined module. It sets up the clock, reset, and input signals, and checks the output against expected values.

Usage

1. Prerequisites:
   • Xilinx Vivado
2. Simulation:
   • Open the project in Vivado.
   • Run the tb_gf16_poly_eval_pipelined testbench to simulate the design.

   # Set up simulation environment
   open_project <your_project>.xpr
   launch_simulation
   run all
   

Simulation Waveform

The simulation waveform illustrates the behavior of the design over time. Key signals include clk, rst, x, C1, and result. The waveform shows the pipelined nature of the design, with the result signal updating after a latency of 14 clock cycles.

Notes

• The BRAM IP cores (blk_mem_gen_0 for XOR and blk_mem_gen_1 for MUL) need to be generated using the Xilinx Vivado IP catalog.
• The latency of the design is 14 clock cycles due to the pipelined architecture.
• The banana module encapsulates the GF(16) multiplication and addition operations.

License

This project is licensed under the Apache License 2.0. See the LICENSE file for details.