This Bachelor's End Project (BEP) at TU/e focuses on developing and characterizing a simplified gold-bump flip-chip bonding process for RF integrated circuit applications. The project demonstrates a cost-effective alternative to traditional multilayer metal stacks by using a single-layer Ti/Au Ground-Signal-Ground (GSG) coplanar waveguide interposer on glass substrates.
- Single-layer simplification: Uses only 50nm Ti/100nm Au metallization instead of complex multilayer stacks
- Glass substrate: Low-cost, low-permittivity alternative to expensive ceramic or silicon carriers
- Gold stud bumps: Thermosonic-placed 70ΞΌm gold bumps eliminate need for solder and under-bump metallurgy
- In-house process: Complete fabrication flow achievable with standard university equipment
π tue-bep/
βββ π amplifier_die/ # RF amplifier component specifications and data
βββ π final_pics_for_paper/ # High-quality images and plots for documentation
βββ π interposer_klayouts/ # KLayout design files for interposer masks
βββ π qucs_simulations_prj/ # RF circuit simulations and modeling
βββ π s_params_and_scripts/ # S-parameter measurements and analysis scripts
βββ π rf_die/ # RF IC die specifications and layouts
βββ π references/ # Research papers and technical references
βββ π markdown_notes_and_files/ # Project documentation and progress notes
Successfully developed a complete flip-chip bonding process:
- Gold stud bump formation using thermosonic wire bonding
- Thermo-compression flip-chip assembly
- High interconnect yield achieved
Comprehensive RF measurements from 10 MHz to 10 GHz:
- Developed lumped circuit model for gold bump behavior
- Validated Ο-model for GSG transmission lines on glass
- Created de-embedding methodology for accurate measurements
Achieved high-yield flip-chip assembly:
- Statistical analysis of bond success rates
- Process parameter optimization
- Damage-free assembly of thin RF dies
- Substrate: Glass with Ξ΅α΅£ = 7.75
- Metallization: 50nm Ti / 100nm Au single layer
- Trace geometry: Ground-Signal-Ground coplanar waveguide
- Impedance: 50Ξ© characteristic impedance
- Height: 70ΞΌm
- Formation: Thermosonic wire bonding process
- Material: Pure gold studs
- Pitch: Compatible with standard RF IC pad layouts
- Frequency range: 10 MHz - 10 GHz
- Characteristic impedance: 49.8Ξ© (simulated vs measured)
- Low-frequency behavior: Simple series resistance model
- Validated models: Ready for PDK integration
- Thermosonic wire bonder: For gold stud bump formation
- Dr. Tresky T-5300: Flip-chip thermo-compression bonding
- KLayout: Mask design and layout verification
- Clean room facilities: TU/e Flux lab
- Vector Network Analyzer (VNA): Broadband S-parameter measurements
- GSG probes: Ground-Signal-Ground RF probing
- Microscopy: Process monitoring and yield analysis
- QUCS: RF circuit simulation and modeling
- Lumped element extraction: RLC bump models
- Transmission line modeling: Ο-equivalent circuits
- Analytical modeling: Closed-form equations for CPWG on glass
- Circuit simulation: QUCS-based system modeling
- Layout design: KLayout mask generation
- Fabrication: In-house processing
- Measurement: VNA-based RF characterization
- Model validation: Simulation vs measurement comparison
- Multi-technology integration: Combine CMOS, InP, and legacy processes
- Automotive radar: High-frequency automotive applications
- Wireless communication: Broadband RF systems
- Cost reduction: Glass substrate alternative to expensive carriers
- Process Design Kit (PDK): Validated models for circuit design
- Prototyping platform: Cost-effective RF SiP development
- Educational tool: Complete flip-chip process demonstration
Student: Daniel Tyukov (d.tyukov@student.tue.nl)
Supervisors:
- M. Fattori (Primary supervisor)
- G. Radulov
- T. Matray
- V. Vidojkovic (Technical assistance)
- V. Zaoutis (Technical assistance)
Institution: Integrated Circuits Group, Department of Electrical Engineering, Eindhoven University of Technology
Duration: February 13, 2025 - June 11, 2025
- Title: "Development and Characterization of a Gold-Bump Flip-Chip Bonding Process for RF IC Applications"
- Venue: SIITME 2025 (submitted)
- Keywords: flip-chip bonding, gold stud bumps, Ti/Au CPWG interposer, thermosonic bonding, RF SiP
- Complete process documentation
- Validated circuit models for PDK integration
- Statistical yield analysis
- Open-source design files and simulation models
- KLayout for mask design
- QUCS for circuit simulation
- Vector Network Analyzer for measurements
- Access to wire bonding and flip-chip equipment
interposer_klayouts/: Design files for glass interposer masksqucs_simulations_prj/: Circuit models and simulationss_params_and_scripts/: Measurement data and analysisfinal_pics_for_paper/: Documentation images and plots
- Open QUCS project files for circuit modeling
- Review KLayout designs for interposer geometry
- Analyze S-parameter data for model validation
- Compare simulation results with measurements
- Bump height optimization: Investigate different stud geometries
- Thermal profile tuning: Optimize thermo-compression parameters
- Yield enhancement: Statistical process optimization
- Higher frequencies: Extend characterization beyond 10 GHz
- Multi-chip assemblies: Demonstrate SiP integration
- Alternative substrates: Investigate silicon and ceramic options
- Advanced modeling: Include parasitic effects and nonlinearities
This project is developed as part of academic research at TU/e. Design files and documentation are provided for educational and research purposes. For commercial applications, please contact the project supervisors.
This project demonstrates the feasibility of cost-effective flip-chip bonding for RF applications using simplified processing and standard university equipment. The validated models and process documentation enable future researchers to build upon this foundation for advanced RF System-in-Package development.