C5: enable CPU-controlled SPI

[bugadani]

Closes #4740

[Copilot]

Pull request overview

Enables CPU-controlled SPI support for ESP32-C5 across the HAL and metadata system, including the clocking differences (PCR pre-divider) and HIL coverage updates, addressing “Stable SPI” for C5 (closes #4740).

Changes:

• Add ESP32-C5 SPI metadata (SPI2 instances, clock nodes, and new has_clk_pre_div capability flag) and regenerate metadata outputs.
• Update esp-hal SPI master clock-source handling for PCR-based SoCs and document C5’s effective SPI clocking.
• Enable existing SPI HIL tests to run on ESP32-C5 and update docs/changelog to reflect C5 SPI support.

Reviewed changes

Copilot reviewed 17 out of 19 changed files in this pull request and generated 5 comments.

Show a summary per file

File	Description
hil-test/src/bin/spi_half_duplex_slave_qspi.rs	Adds esp32c5 to the chip matrix for this HIL test binary.
hil-test/src/bin/spi_full_duplex.rs	Adds esp32c5 to the chip matrix and adjusts expected master clock for C5 in clock-accuracy test.
esp-metadata/src/cfg.rs	Extends SPI master properties with has_clk_pre_div and allows multiple attributes per property in the macro.
esp-metadata/devices/esp32c5.toml	Declares SPI master/slave instances for C5 and introduces the C5-specific clocking capability flag.
esp-metadata-generated/src/_generated_esp32s3.rs	Adds generated spi_master.has_clk_pre_div = false.
esp-metadata-generated/src/_generated_esp32s2.rs	Adds generated spi_master.has_clk_pre_div = false.
esp-metadata-generated/src/_generated_esp32h2.rs	Adds generated spi_master.has_clk_pre_div = false.
esp-metadata-generated/src/_generated_esp32c6.rs	Adds generated spi_master.has_clk_pre_div = false.
esp-metadata-generated/src/_generated_esp32c5.rs	Generates C5 SPI properties/macros and adds peripheral clock controls for DMA/SPI2.
esp-metadata-generated/src/_generated_esp32c3.rs	Adds generated spi_master.has_clk_pre_div = false.
esp-metadata-generated/src/_generated_esp32c2.rs	Adds generated spi_master.has_clk_pre_div = false.
esp-metadata-generated/src/_generated_esp32.rs	Adds generated spi_master.has_clk_pre_div = false.
esp-metadata-generated/src/_build_script_utils.rs	Emits new cfg symbol spi_master_has_clk_pre_div and enables SPI master/slave cfgs for C5.
esp-hal/src/spi/master.rs	Updates SPI master clock source selection/init for C5 and PCR-based SoCs (pre-divider handling).
esp-hal/src/lib.rs	Removes an ESP32-C5-specific expect(unused) attribute (no longer needed).
esp-hal/src/gpio/interconnect.rs	Removes an ESP32-C5-specific expect(unused) attribute (no longer needed).
esp-hal/src/clock/mod.rs	Removes an ESP32-C5-specific expect(dead_code) attribute (no longer needed).
esp-hal/README.md	Updates the feature support table to show SPI master availability on ESP32-C5.
esp-hal/CHANGELOG.md	Adds a changelog entry noting ESP32-C5 SPI support.

[Copilot]

Pull request overview

Copilot reviewed 19 out of 21 changed files in this pull request and generated 2 comments.

Comments suppressed due to low confidence (1)

esp-hal/src/spi/master.rs:3824

• This comment says the default PCR clock source is PLL_F80M_CLK, but this code now applies to all soc_has_pcr chips (including ESP32-H2 and ESP32-C5) where the selected/default source differs. Reword this to something source-agnostic (e.g., “use PCR-configured clock source”) or make it conditional per chip to avoid misleading documentation.

        #[cfg(soc_has_pcr)]
        // use default clock source PLL_F80M_CLK
        crate::peripherals::PCR::regs()
            .spi2_clkm_conf()
            .modify(|_, w| unsafe { w.spi2_clkm_sel().bits(1) });

[Copilot]

Pull request overview

Copilot reviewed 19 out of 21 changed files in this pull request and generated no new comments.

[bugadani]

/hil esp32c5

[github-actions]

Triggered HIL run for #4943 (chips: esp32c5).

Run: https://github.com/esp-rs/esp-hal/actions/runs/21873778588

Status update: HIL (per-chip) run is still in progress or status unknown.

[Copilot]

Pull request overview

Copilot reviewed 18 out of 20 changed files in this pull request and generated 1 comment.

Comments suppressed due to low confidence (1)

esp-hal/src/spi/master.rs:3826

• setup_half_duplex configures PCR::spi2_clkm_conf differently than init() (it only sets spi2_clkm_sel, and does not set spi2_clkm_en / spi2_clkm_div_num when spi_master_has_clk_pre_div is enabled). This duplication makes it easy for the two paths to drift and can break ESP32-C5 if the PCR clock config is ever reset/reinitialized outside init(). Consider factoring PCR clock setup into a shared helper and applying the same divider/enable logic in both places.

        #[cfg(soc_has_pcr)]
        // use default clock source
        crate::peripherals::PCR::regs()
            .spi2_clkm_conf()
            .modify(|_, w| unsafe { w.spi2_clkm_sel().bits(1) });