esp32c5: enable RMT metadata and clock initialization

[Veanir]

Summary

• add missing ESP32-C5 RMT metadata ([device.rmt]) and include Rmt in peripheral clock generation so rmt_driver_supported and channel/clock-source macros are emitted
• regenerate esp-metadata-generated outputs for ESP32-C5 and refresh the chip support table in esp-hal/README.md
• initialize C5-specific RMT runtime prerequisites in esp-hal/src/rmt.rs by forcing RMT memory power-up (RMT_PD_CTRL) and enabling RMT_SCLK_CONF.SCLK_EN

Verification

• cargo xtask update-metadata
• cargo +esp check --manifest-path esp-hal/Cargo.toml --features esp32c5,unstable -Zbuild-std=core --target riscv32imac-unknown-none-elf
• cargo +esp check --manifest-path esp-hal/Cargo.toml --features esp32c6,unstable -Zbuild-std=core --target riscv32imac-unknown-none-elf
• cargo check --manifest-path esp-metadata-generated/Cargo.toml

[Copilot]

Pull request overview

Enables ESP32-C5 RMT support in esp-hal by adding missing chip metadata and ensuring the RMT peripheral clock + runtime prerequisites are initialized so the RMT driver and associated macros/config are emitted and functional.

Changes:

• Add ESP32-C5 [device.rmt] metadata and include Rmt in peripheral clock generation.
• Regenerate esp-metadata-generated outputs for ESP32-C5 (properties, peripheral clocks, and RMT helper macros/cfgs).
• Add ESP32-C5-specific RMT runtime initialization (force RMT memory power-up and enable RMT SCLK).

Reviewed changes

Copilot reviewed 5 out of 5 changed files in this pull request and generated no comments.

Show a summary per file

File	Description
esp-metadata/devices/esp32c5.toml	Adds RMT device metadata and includes Rmt in clock/peripheral generation inputs for ESP32-C5.
esp-metadata-generated/src/_generated_esp32c5.rs	Regenerated chip outputs: RMT properties, peripheral clock enum/control, and RMT channel/clock-source macros.
esp-metadata-generated/src/_build_script_utils.rs	Regenerated build-script cfg emissions for ESP32-C5 to include rmt_driver_supported and RMT-related cfgs.
esp-hal/src/rmt.rs	Adds ESP32-C5 RMT hardware prerequisites during clock configuration (memory power + SCLK enable).
esp-hal/README.md	Updates the chip support table to reflect ESP32-C5 RMT availability.

[Copilot]

Pull request overview

Copilot reviewed 5 out of 5 changed files in this pull request and generated no new comments.

[MabezDev]

Thanks for the PR!

Could you also enable the RMT HIL tests for esp32c5, then we can run it here.

[MabezDev]

/hil esp32c5

[github-actions]

Triggered HIL run for #4964 (chips: esp32c5).

Run: https://github.com/esp-rs/esp-hal/actions/runs/21912912009

Status update: ❌ HIL (per-chip) run failed (conclusion: failure).

[Veanir]

/hil esp32c5

[github-actions]

@Veanir, sorry — you're not allowed to execute HIL runs or binary size analysis for this PR.
Please ask an esp-rs member/owner to grant access with:

/trust @Veanir

After that, you can use /hil quick, /hil full, /hil <chips...> or /test-size.

[Veanir]

Pushed follow-up fix e8963b8: on ESP32-C5, pulse ref_cnt_rst for the active channel before start_tx/start_rx (matching IDF LL behavior). Local preflight builds pass for esp32c5 and esp32c6 RMT HIL binaries. Bot says I'm not trusted to run /hil on this PR yet; could an esp-rs member run /trust @Veanir once, then /hil esp32c5?

[bugadani]

/hil full

[github-actions]

Triggered full HIL run for #4964.

Run: https://github.com/esp-rs/esp-hal/actions/runs/21916426153

Status update: ❌ HIL (full) run failed (conclusion: failure).

[bugadani]

Could you post espflash board-info for your C5 please?

[Veanir]

Thanks for checking. Here is espflash board-info from the ESP32-C5 board I used for local verification of this PR head (e8963b81):

- Chip type: `esp32c5 (revision v1.0)`
- Crystal frequency: `48 MHz`
- Flash size: `8MB`
- Features: `WiFi, BLE, IEEE802.15.4, 240MHz`
- Chip ID: `23`
- Secure Boot: `Disabled`
- Flash Encryption: `Disabled`

Local verification on the same commit:

- `cargo xtask run tests esp32c5 --test rmt --toolchain nightly` -> `20 passed; 0 failed`
- `cargo xtask run tests esp32c5 --test rmt --repeat 5 --toolchain nightly` -> `5/5 runs passed`
- CI-like flow also passes locally:
  - `cargo xtask build tests esp32c5 --test rmt --toolchain nightly`
  - `cargo xtask run elfs esp32c5 target/tests/esp32c5 --elfs rmt`

Environment:

- Board connected via USB-Serial-JTAG (`ESP32-C5-DevKitC-1`)
- `probe-rs 0.31.0`

[bugadani]

Running the tests successfully needs power-cycling the target. We persist some state from one of the other tests that interferes here. At this point I consider this a probe-rs issue, and not something to be addressed in this PR.

[Copilot]

Pull request overview

Copilot reviewed 5 out of 6 changed files in this pull request and generated no new comments.

[Copilot]

Pull request overview

Copilot reviewed 6 out of 7 changed files in this pull request and generated no new comments.

[bugadani]

You don't have to keep rebasing this PR. Once we have a solution for the test issue, we'll either do it ourselves or ping you for it. It'll take a bit of time, though, hope you don't mind leaving this hanging for a few days.

[Veanir]

Thanks for the heads-up! No worries - I’m still getting used to workflow here, so I appreciate the guidance.
Ping me when you’re ready or if you’d like me to tweak anything.