⚙️ Computer Organization and Systems (ETU "LETI")

This repository contains research and low-level implementations focused on computer architecture and hardware-software interaction.

🤝 Collaboration

These projects were completed in collaboration with my teammate Nikita Bulkin. We practiced pair programming and joint research on processor microarchitecture.

🔬 Key Topics Explored

• ISA RISC-V: Writing assembly code for RV32I/RV32IM.
• Memory Hierarchy: Analyzing L1 Cache hit/miss strategies and performance.
• Peripheral Interfacing: Directly manipulating memory-mapped I/O for visual output.
• Pipeline Analysis: Debugging data hazards and control hazards in a 5-stage processor pipeline using the Ripes simulator.
• Data Representation: Endianness (Little-endian), cross-compilation from C to RISC-V.

📁 Repository Structure

Each folder contains the Assembly source code (.txt/.s) and a detailed technical report (.docx) with execution analysis and pipeline diagrams.