crc: crc32_iscsi_by16_10 opt for short data #380
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@pablodelara Hi, sorry to bother. This pull request has been created for some time. I was wondering if there is anything we could do to improve this work? |
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Two minor comments, thanks!
| je .exact_16_left | ||
| jl .less_than_16_left | ||
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| vmovdqu xmm7, [arg2] ; load the plaintext |
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Could you add a comment saying there are a between 17 and 32 bytes at this stage?
| add arg2,2 | ||
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| .less_than_2: | ||
| test arg3,1 ; check if 1 byte remaining |
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Might be shorter to do "or arg3,arg3"
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Sorry, but the test instr in other labels before will not change the result of arg3. If arg3 is 0b10, after processed in less_than_4, arg3 keeps the value of 0b10. Then or arg3, arg3 will lead to a incorrect not-taken branch. So we had to check only the least significant bit.
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- Add fastpath for short data - Change code align from 16 to 64 - Code reordering when dealing final 16 bytes after folding Signed-off-by: Maodi Ma <mamaodi@hygon.cn>
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This PR is merged now, thanks! |
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This pull request contains 3 modifications:
Part 1: Do the same thing as part of https://github.com/intel/isa-l/pull/375, adding fastpath for short data. The threshold is changed to 8 bytes based on tested performance.
Part 2: Change the entrance alignment of
crc32_iscsi_by16_10from 16 to 64. This improves bandwidth about 5%-17% on our Intel(R) Xeon(R) Platinum 8480+ platform for short data under 16 bytes. But it does no impact on AMD or Hygon platform.Part 3: Adjust the ordering of some instructions in
128_done. This brings ~5% improvement on Hygon platform for scenarios that highly depend on it, like 17-31 bytes. This does no impact on Intel or AMD platform.This commit has no affect on long data processing.
Performance data are listed below (iteration/s):
Only 15 bytes scenario on Hygon platform got a negtive affect. Overall, the performance got improved.
Besides, you can see there is improvement for data longer than 32 bytes only on Intel platform. That is 64 bytes alignment working.