[FIRRTL] Add ReadDesignConfigInt intrinsic for post-Verilog configuration

This patch introduces a new FIRRTL intrinsic `circt.read_design_config_int` that enables post-Verilog configuration by generating a SystemVerilog package (DesignConfigPackage) containing configurable parameters. The intrinsic allows hardware designs to reference configuration values that can be modified after Verilog generation without requiring recompilation.

The implementation includes three main components. First, the ReadDesignConfigIntIntrinsicOp operation takes a parameter name, default value, and optional comment, returning an integer value. Second, the LowerToHW pass converts these intrinsics to sv.localparam operations that reference the generated package using the syntax `DesignConfigPackage::param_name`. Third, the CreateDesignConfigPackage pass collects all configuration parameters from modules under the effective DUT, generates a SystemVerilog package with parameter declarations, and creates OM metadata for tooling integration.

Configuration parameters are only generated for the effective DUT to avoid conflicts when compiling testbenches separately. The generated package uses standard SystemVerilog parameter syntax, allowing values to be overridden through compilation flags or configuration files without regenerating the design.

Author: uenoku

include/circt/Dialect/FIRRTL/FIRRTLIntrinsics.td

@@ -243,4 +243,39 @@ def ViewIntrinsicOp : FIRRTLOp<"view", []> {
   let assemblyFormat = "$name `,` (`yaml` $yamlFile^ `,`)? $augmentedType (`,` $inputs^)? attr-dict (`:` type($inputs)^)?";
 }
 
+def ReadDesignConfigIntIntrinsicOp : FIRRTLOp<"int.read_design_config_int",
+    [HasCustomSSAName, Pure]> {
+  let summary = "Read an integer design configuration value";
+  let description = [{
+    The `int.read_design_config_int` intrinsic reads an integer design
+    configuration value that will be defined in a generated configuration package
+    (DesignConfigPackage). This enables post-Verilog configuration where
+    configuration values can be set after Verilog generation.
+
+    The intrinsic takes a parameter name, default value, comment, and
+    a result type. It returns the default value, but the actual value can be
+    changed via the generated configuration package.
+
+    Example usage in FIRRTL:
+    ```
+    %value = firrtl.int.read_design_config_int "buffer_type", 3, "Buffer type selection" : !firrtl.uint<8>
+    ```
+
+    This generates Verilog like:
+    ```verilog
+    localparam buffer_type = DesignConfigPackage::buffer_type;
+    ```
+  }];
+
+  let arguments = (ins
+    StrAttr:$paramName,
+    I64Attr:$defaultValue,
+    StrAttr:$comment
+  );
+  let results = (outs IntType:$result);
+  let assemblyFormat = [{
+    $paramName `,` $defaultValue `,` $comment attr-dict `:` type($result)
+  }];
+}
+
 #endif // CIRCT_DIALECT_FIRRTL_FIRRTLINTRINSICS_TD

include/circt/Dialect/FIRRTL/FIRRTLVisitors.h

@@ -57,6 +57,7 @@ class ExprVisitor {
             LTLImplicationIntrinsicOp, LTLUntilIntrinsicOp,
             LTLEventuallyIntrinsicOp, LTLClockIntrinsicOp, Mux2CellIntrinsicOp,
             Mux4CellIntrinsicOp, HasBeenResetIntrinsicOp,
+            ReadDesignConfigIntIntrinsicOp,
             // Miscellaneous.
             BitsPrimOp, HeadPrimOp, MuxPrimOp, PadPrimOp, ShlPrimOp, ShrPrimOp,
             TailPrimOp, VerbatimExprOp, HWStructCastOp, BitCastOp, RefSendOp,
@@ -190,6 +191,7 @@ class ExprVisitor {
   HANDLE(Mux4CellIntrinsicOp, Unhandled);
   HANDLE(Mux2CellIntrinsicOp, Unhandled);
   HANDLE(HasBeenResetIntrinsicOp, Unhandled);
+  HANDLE(ReadDesignConfigIntIntrinsicOp, Unhandled);
 
   // Miscellaneous.
   HANDLE(BitsPrimOp, Unhandled);

include/circt/Dialect/FIRRTL/Passes.td

@@ -961,5 +961,31 @@ def AnnotateInputOnlyModules : Pass<"firrtl-annotate-input-only-modules",
   ];
 }
 
+def CreateDesignConfigPackage : Pass<"firrtl-create-design-config-package",
+                                     "firrtl::CircuitOp"> {
+  let summary = "Create design configuration package for post-Verilog configuration";
+  let description = [{
+    This pass accumulates all ReadDesignConfigInt intrinsics in the design
+    and generates a SystemVerilog package (DesignConfigPackage) containing
+    all the configuration values. It also creates an OM class with metadata
+    about the configurations.
+
+    The pass only generates the package for the effective DUT (Design Under Test).
+    Configuration values are collected from all modules instantiated under the DUT.
+
+    The generated package can be used for post-Verilog configuration by
+    modifying the configuration values without regenerating the Verilog.
+  }];
+  let dependentDialects = [
+    "emit::EmitDialect",
+    "hw::HWDialect",
+    "sv::SVDialect",
+    "om::OMDialect"
+  ];
+  let statistics = [
+    Statistic<"numConfigs", "num-configs", "Number of configurations collected">
+  ];
+}
+
 
 #endif // CIRCT_DIALECT_FIRRTL_PASSES_TD

lib/Conversion/FIRRTLToHW/LowerToHW.cpp

@@ -2039,6 +2039,7 @@ struct FIRRTLLowering : public FIRRTLVisitor<FIRRTLLowering, LogicalResult> {
   LogicalResult visitExpr(LTLUntilIntrinsicOp op);
   LogicalResult visitExpr(LTLEventuallyIntrinsicOp op);
   LogicalResult visitExpr(LTLClockIntrinsicOp op);
+  LogicalResult visitExpr(ReadDesignConfigIntIntrinsicOp op);
 
   template <typename TargetOp, typename IntrinsicOp>
   LogicalResult lowerVerifIntrinsicOp(IntrinsicOp op);
@@ -4524,6 +4525,36 @@ LogicalResult FIRRTLLowering::visitExpr(HasBeenResetIntrinsicOp op) {
   return setLoweringTo<verif::HasBeenResetOp>(op, clock, reset, isAsync);
 }
 
+LogicalResult
+FIRRTLLowering::visitExpr(ReadDesignConfigIntIntrinsicOp op) {
+  // Lower the ReadDesignConfigInt intrinsic to sv.localparam that
+  // references the configuration from DesignConfigPackage.
+  //
+  // Example:
+  //   %value = firrtl.int.read_design_config_int "buffer_type", 3, "comment"
+  //     : !firrtl.uint<8>
+  //
+  // Lowers to:
+  //   %value = sv.localparam : i8 {
+  //     value = #hw.param.verbatim<"DesignConfigPackage::buffer_type"> : i8
+  //   }
+
+  auto resultType = lowerType(op.getResult().getType());
+  if (!resultType)
+    return failure();
+
+  // Create a verbatim reference to the configuration in DesignConfigPackage
+  std::string paramRef = "DesignConfigPackage::" + op.getParamName().str();
+  auto paramVerbatim = hw::ParamVerbatimAttr::get(
+      builder.getStringAttr(paramRef), resultType);
+
+  // Create sv.localparam operation with the configuration reference
+  auto localParam = builder.create<sv::LocalParamOp>(
+      op.getLoc(), resultType, paramVerbatim, op.getParamNameAttr());
+
+  return setLowering(op, localParam);
+}
+
 //===----------------------------------------------------------------------===//
 // Other Operations
 //===----------------------------------------------------------------------===//

lib/Dialect/FIRRTL/FIRRTLIntrinsics.cpp

@@ -881,6 +881,48 @@ parseAugmentedType(MLIRContext *context, Location loc,
   return std::nullopt;
 }
 
+class CirctReadDesignConfigIntConverter : public IntrinsicConverter {
+public:
+  using IntrinsicConverter::IntrinsicConverter;
+
+  bool check(GenericIntrinsic gi) override {
+    // Check that we have no inputs, an integer output type, and 3 parameters
+    if (gi.hasNInputs(0))
+      return true;
+
+    if (!type_isa<IntType>(gi.op.getResult().getType())) {
+      gi.emitError() << "result must be an integer type";
+      return true;
+    }
+
+    if (gi.namedParam("name") || gi.namedIntParam("defaultValue") ||
+        gi.namedParam("comment"))
+      return true;
+
+    if (gi.hasNParam(3))
+      return true;
+
+    return false;
+  }
+
+  void convert(GenericIntrinsic gi, GenericIntrinsicOpAdaptor adaptor,
+               PatternRewriter &rewriter) override {
+    auto paramName = gi.getParamValue<StringAttr>("name");
+    auto defaultValueAttr = gi.getParamValue<IntegerAttr>("defaultValue");
+
+    // Convert the defaultValue to i64
+    auto defaultValue = rewriter.getI64IntegerAttr(
+        defaultValueAttr.getValue().getSExtValue());
+
+    auto comment = gi.getParamValue<StringAttr>("comment");
+
+    auto resultType = gi.op.getResult().getType();
+
+    rewriter.replaceOpWithNewOp<ReadDesignConfigIntIntrinsicOp>(
+        gi.op, resultType, paramName, defaultValue, comment);
+  }
+};
+
 class ViewConverter : public IntrinsicConverter {
 public:
   LogicalResult checkAndConvert(GenericIntrinsic gi,

lib/Dialect/FIRRTL/FIRRTLIntrinsics.td

@@ -65,3 +65,28 @@ def CirctIsX : FIRRTLIntrinsic {
     | found  | UInt<1> | i is `x`    |
   }];
 }
+
+def CirctReadDesignConfigInt : FIRRTLIntrinsic {
+  let mnemonic = "circt.read_design_config_int";
+  let converter = "CirctReadDesignConfigIntConverter";
+  let description = [{
+    Reads an integer design configuration value that will be defined in a
+    generated configuration package. This intrinsic is used for post-Verilog
+    configuration, where configuration values can be set after Verilog generation.
+
+    The generated Verilog will reference the configuration from DesignConfigPackage:
+    ```verilog
+    localparam buffer_type = DesignConfigPackage.buffer_type;
+    ```
+
+    | Parameter    | Type   | Description                                  |
+    | ------------ | ------ | -------------------------------------------- |
+    | name         | String | Name of the configuration                    |
+    | defaultValue | Int    | Default value of the configuration           |
+    | comment      | String | Description of the configuration (can be empty) |
+
+    | Result | Type | Description                                |
+    | ------ | ---- | ------------------------------------------ |
+    | value  | Int  | The configuration value                    |
+  }];
+}

lib/Dialect/FIRRTL/FIRRTLOps.cpp

@@ -6462,6 +6462,10 @@ void AndRPrimOp::getAsmResultNames(OpAsmSetValueNameFn setNameFn) {
 void SizeOfIntrinsicOp::getAsmResultNames(OpAsmSetValueNameFn setNameFn) {
   genericAsmResultNames(*this, setNameFn);
 }
+void ReadDesignConfigIntIntrinsicOp::getAsmResultNames(
+    OpAsmSetValueNameFn setNameFn) {
+  setNameFn(getResult(), getParamName());
+}
 void AsAsyncResetPrimOp::getAsmResultNames(OpAsmSetValueNameFn setNameFn) {
   genericAsmResultNames(*this, setNameFn);
 }

lib/Dialect/FIRRTL/Transforms/CMakeLists.txt

@@ -7,6 +7,7 @@ add_circt_dialect_library(CIRCTFIRRTLTransforms
   CheckLayers.cpp
   CheckRecursiveInstantiation.cpp
   CreateSiFiveMetadata.cpp
+  CreateDesignConfigPackage.cpp
   Dedup.cpp
   DropConst.cpp
   DropName.cpp