[LLHD] Assigning a signal to itself makes Sig2Reg hang

[m2kar]

Description

CIRCT hangs indefinitely when processing invalid SystemVerilog code that has both procedural (non-blocking) and continuous assignments to the same signal. Other tools (Verilator, Icarus Verilog) correctly reject this code with an error message. CIRCT should detect this invalid pattern and report an error instead of hanging.

Steps to Reproduce

1. Save the following code as bug.sv
2. Run: circt-verilog --ir-hw bug.sv
3. Observe: Compiler hangs indefinitely (no output, no error message)

Test Case

module bug(input logic clk, output logic q);
  logic d;

  always @(negedge clk) begin
    q <= d;  // Non-blocking procedural assignment
  end

  assign q = q;  // Continuous assignment to same signal
endmodule

Expected Behavior

CIRCT should reject this code with an error message similar to:

error: Cannot perform procedural assignment to variable 'q' because it is also continuously assigned

Actual Behavior

v1.139.0:

Compiler hangs indefinitely in the LLHD Sig2Reg pass (no output after 60+ seconds).

$ circt-verilog --ir-hw bug.sv
[1]    1623059 terminated  circt-verilog --ir-hw bug.sv

(manually killed after 60+ seconds)

$ circt-verilog --version
LLVM (http://llvm.org/):
  LLVM version 22.0.0git
  Optimized build.
CIRCT firtool-1.139.0
slang version 9.1.0+0

main branch (commit e4838c7)

However, in the main branch (commit e4838c7), the compiler crashes with a stack dump instead. This leaves uncertainty about whether the hang has been fixed or merely replaced with a different failure mode.

$ circt-verilog --ir-hw bug.sv 
bug.sv:8:14: error: 'llhd.prb' op operation destroyed but still has uses
  assign q = q;  // Combinational loop
             ^
bug.sv:8:14: note: see current operation: %0 = "llhd.prb"(<<UNKNOWN SSA VALUE>>) : (!llhd.ref<i1>) -> i1
bug.sv:1:8: note: - use: "hw.output"(<<UNKNOWN SSA VALUE>>) : (i1) -> ()

module bug(input logic clk, output logic q);
       ^
LLVM ERROR: operation destroyed but still has uses
PLEASE submit a bug report to https://github.com/llvm/circt and include the crash backtrace.
Stack dump:
0.      Program arguments: /root/circt/build/bin/circt-verilog --ir-hw bug.sv
 #0 0x00005607819e0738 llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) /root/circt/llvm/llvm/lib/Support/Unix/Signals.inc:842:13
 #1 0x00005607819de333 llvm::sys::RunSignalHandlers() /root/circt/llvm/llvm/lib/Support/Signals.cpp:109:18
 #2 0x00005607819e1471 SignalHandler(int, siginfo_t*, void*) /root/circt/llvm/llvm/lib/Support/Unix/Signals.inc:429:38
 #3 0x00007f30dec7b330 (/lib/x86_64-linux-gnu/libc.so.6+0x45330)
 #4 0x00007f30decd4b2c __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
 #5 0x00007f30decd4b2c __pthread_kill_internal ./nptl/pthread_kill.c:78:10
 #6 0x00007f30decd4b2c pthread_kill ./nptl/pthread_kill.c:89:10
 #7 0x00007f30dec7b27e raise ./signal/../sysdeps/posix/raise.c:27:6
 #8 0x00007f30dec5e8ff abort ./stdlib/abort.c:81:7
 #9 0x00005607819a7cd7 llvm::report_fatal_error(llvm::Twine const&, bool) /root/circt/llvm/llvm/lib/Support/ErrorHandling.cpp:137:5
#10 0x00005607819a7b26 (/root/circt/build/bin/circt-verilog+0xff3b26)
#11 0x000056078109dec6 mlir::InFlightDiagnostic::attachNote(std::optional<mlir::Location>) /root/circt/llvm/mlir/include/mlir/IR/Diagnostics.h:366:5
#12 0x000056078109dec6 mlir::Operation::~Operation() /root/circt/llvm/mlir/lib/IR/Operation.cpp:187:14
#13 0x000056078109ea7d mlir::Operation::destroy() /root/circt/llvm/mlir/lib/IR/Operation.cpp:214:3
#14 0x000056078109ea7d llvm::ilist_traits<mlir::Operation>::deleteNode(mlir::Operation*) /root/circt/llvm/mlir/lib/IR/Operation.cpp:487:7
#15 0x0000560780ca030e llvm::iplist_impl<llvm::simple_ilist<mlir::Operation>, llvm::ilist_traits<mlir::Operation>>::erase(llvm::ilist_iterator<llvm::ilist_detail::node_options<mlir::Operation, true, false, void, false, void>, false, false>) /root/circt/llvm/llvm/include/llvm/ADT/ilist.h:206:5
#16 0x0000560780ca2e7a bool std::operator==<mlir::Operation**>(std::reverse_iterator<mlir::Operation**> const&, std::reverse_iterator<mlir::Operation**> const&) /usr/lib/gcc/x86_64-linux-gnu/13/../../../../include/c++/13/bits/stl_iterator.h:450:25
#17 0x0000560780ca2e7a bool std::operator!=<mlir::Operation**>(std::reverse_iterator<mlir::Operation**> const&, std::reverse_iterator<mlir::Operation**> const&) /usr/lib/gcc/x86_64-linux-gnu/13/../../../../include/c++/13/bits/stl_iterator.h:464:20
#18 0x0000560780ca2e7a (anonymous namespace)::SigPromoter::promote() /root/circt/lib/Dialect/LLHD/Transforms/Sig2RegPass.cpp:293:19
#19 0x0000560780ca2e7a (anonymous namespace)::Sig2RegPass::runOnOperation() /root/circt/lib/Dialect/LLHD/Transforms/Sig2RegPass.cpp:368:14
#20 0x0000560781827df2 mlir::detail::OpToOpPassAdaptor::run(mlir::Pass*, mlir::Operation*, mlir::AnalysisManager, bool, unsigned int)::$_3::operator()() const /root/circt/llvm/mlir/lib/Pass/Pass.cpp:0:19
#21 0x0000560781827df2 void llvm::function_ref<void ()>::callback_fn<mlir::detail::OpToOpPassAdaptor::run(mlir::Pass*, mlir::Operation*, mlir::AnalysisManager, bool, unsigned int)::$_3>(long) /root/circt/llvm/llvm/include/llvm/ADT/STLFunctionalExtras.h:46:12
#22 0x0000560781827df2 llvm::function_ref<void ()>::operator()() const /root/circt/llvm/llvm/include/llvm/ADT/STLFunctionalExtras.h:69:12
#23 0x0000560781827df2 void mlir::MLIRContext::executeAction<mlir::PassExecutionAction, mlir::Pass&>(llvm::function_ref<void ()>, llvm::ArrayRef<mlir::IRUnit>, mlir::Pass&) /root/circt/llvm/mlir/include/mlir/IR/MLIRContext.h:290:7
#24 0x0000560781827df2 mlir::detail::OpToOpPassAdaptor::run(mlir::Pass*, mlir::Operation*, mlir::AnalysisManager, bool, unsigned int) /root/circt/llvm/mlir/lib/Pass/Pass.cpp:606:23
#25 0x0000560781828ab4 mlir::detail::OpToOpPassAdaptor::runPipeline(mlir::OpPassManager&, mlir::Operation*, mlir::AnalysisManager, bool, unsigned int, mlir::PassInstrumentor*, mlir::PassInstrumentation::PipelineParentInfo const*) /root/circt/llvm/mlir/lib/Pass/Pass.cpp:688:9
#26 0x0000560781833282 mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::$_12::operator()(mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::OpPMInfo&) const /root/circt/llvm/mlir/lib/Pass/Pass.cpp:1004:9
#27 0x0000560781833282 auto void mlir::parallelForEach<__gnu_cxx::__normal_iterator<mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::OpPMInfo*, std::vector<mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::OpPMInfo, std::allocator<mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::OpPMInfo>>>, mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::$_12>(mlir::MLIRContext*, __gnu_cxx::__normal_iterator<mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::OpPMInfo*, std::vector<mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::OpPMInfo, std::allocator<mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::OpPMInfo>>>, __gnu_cxx::__normal_iterator<mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::OpPMInfo*, std::vector<mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::OpPMInfo, std::allocator<mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::OpPMInfo>>>, mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::$_12&&)::'lambda'(__gnu_cxx::__normal_iterator<mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::OpPMInfo*, std::vector<mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::OpPMInfo, std::allocator<mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::OpPMInfo>>>&&)::operator()<mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::OpPMInfo&>(__gnu_cxx::__normal_iterator<mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::OpPMInfo*, std::vector<mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::OpPMInfo, std::allocator<mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::OpPMInfo>>>&&) const /root/circt/llvm/mlir/include/mlir/IR/Threading.h:120:12
#28 0x000056078182b39b llvm::LogicalResult mlir::failableParallelForEach<__gnu_cxx::__normal_iterator<mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::OpPMInfo*, std::vector<mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::OpPMInfo, std::allocator<mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::OpPMInfo>>>, void mlir::parallelForEach<__gnu_cxx::__normal_iterator<mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::OpPMInfo*, std::vector<mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::OpPMInfo, std::allocator<mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::OpPMInfo>>>, mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::$_12>(mlir::MLIRContext*, __gnu_cxx::__normal_iterator<mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::OpPMInfo*, std::vector<mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::OpPMInfo, std::allocator<mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::OpPMInfo>>>, __gnu_cxx::__normal_iterator<mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::OpPMInfo*, std::vector<mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::OpPMInfo, std::allocator<mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::OpPMInfo>>>, mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::$_12&&)::'lambda'(__gnu_cxx::__normal_iterator<mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::OpPMInfo*, std::vector<mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::OpPMInfo, std::allocator<mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::OpPMInfo>>>&&)>(mlir::MLIRContext*, __gnu_cxx::__normal_iterator<mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::OpPMInfo*, std::vector<mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::OpPMInfo, std::allocator<mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::OpPMInfo>>>, __gnu_cxx::__normal_iterator<mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::OpPMInfo*, std::vector<mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::OpPMInfo, std::allocator<mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::OpPMInfo>>>, mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::$_12&&) /root/circt/llvm/mlir/include/mlir/IR/Threading.h:0:18
#29 0x000056078182b39b void mlir::parallelForEach<__gnu_cxx::__normal_iterator<mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::OpPMInfo*, std::vector<mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::OpPMInfo, std::allocator<mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::OpPMInfo>>>, mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::$_12>(mlir::MLIRContext*, __gnu_cxx::__normal_iterator<mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::OpPMInfo*, std::vector<mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::OpPMInfo, std::allocator<mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::OpPMInfo>>>, __gnu_cxx::__normal_iterator<mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::OpPMInfo*, std::vector<mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::OpPMInfo, std::allocator<mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::OpPMInfo>>>, mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::$_12&&) /root/circt/llvm/mlir/include/mlir/IR/Threading.h:119:9
#30 0x000056078182b39b void mlir::parallelForEach<std::vector<mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::OpPMInfo, std::allocator<mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::OpPMInfo>>&, mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::$_12>(mlir::MLIRContext*, std::vector<mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::OpPMInfo, std::allocator<mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::OpPMInfo>>&, mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool)::$_12&&) /root/circt/llvm/mlir/include/mlir/IR/Threading.h:131:3
#31 0x000056078182b39b mlir::detail::OpToOpPassAdaptor::runOnOperationAsyncImpl(bool) /root/circt/llvm/mlir/lib/Pass/Pass.cpp:991:3
#32 0x0000560781828037 mlir::detail::OpToOpPassAdaptor::runOnOperation(bool) /root/circt/llvm/mlir/lib/Pass/Pass.cpp:0:5
#33 0x0000560781828037 mlir::detail::OpToOpPassAdaptor::run(mlir::Pass*, mlir::Operation*, mlir::AnalysisManager, bool, unsigned int)::$_3::operator()() const /root/circt/llvm/mlir/lib/Pass/Pass.cpp:610:22
#34 0x0000560781828037 void llvm::function_ref<void ()>::callback_fn<mlir::detail::OpToOpPassAdaptor::run(mlir::Pass*, mlir::Operation*, mlir::AnalysisManager, bool, unsigned int)::$_3>(long) /root/circt/llvm/llvm/include/llvm/ADT/STLFunctionalExtras.h:46:12
#35 0x0000560781828037 llvm::function_ref<void ()>::operator()() const /root/circt/llvm/llvm/include/llvm/ADT/STLFunctionalExtras.h:69:12
#36 0x0000560781828037 void mlir::MLIRContext::executeAction<mlir::PassExecutionAction, mlir::Pass&>(llvm::function_ref<void ()>, llvm::ArrayRef<mlir::IRUnit>, mlir::Pass&) /root/circt/llvm/mlir/include/mlir/IR/MLIRContext.h:290:7
#37 0x0000560781828037 mlir::detail::OpToOpPassAdaptor::run(mlir::Pass*, mlir::Operation*, mlir::AnalysisManager, bool, unsigned int) /root/circt/llvm/mlir/lib/Pass/Pass.cpp:606:23
#38 0x0000560781828ab4 mlir::detail::OpToOpPassAdaptor::runPipeline(mlir::OpPassManager&, mlir::Operation*, mlir::AnalysisManager, bool, unsigned int, mlir::PassInstrumentor*, mlir::PassInstrumentation::PipelineParentInfo const*) /root/circt/llvm/mlir/lib/Pass/Pass.cpp:688:9
#39 0x000056078182f6fb mlir::PassManager::runPasses(mlir::Operation*, mlir::AnalysisManager) /root/circt/llvm/mlir/lib/Pass/Pass.cpp:1123:3
#40 0x000056078182ed7e mlir::PassManager::run(mlir::Operation*) /root/circt/llvm/mlir/lib/Pass/Pass.cpp:1097:0
#41 0x0000560780ab1cad executeWithSources(mlir::MLIRContext*, llvm::SourceMgr&) /root/circt/tools/circt-verilog/circt-verilog.cpp:404:9
#42 0x0000560780aaea1f execute(mlir::MLIRContext*) /root/circt/tools/circt-verilog/circt-verilog.cpp:481:10
#43 0x0000560780aae0c8 main /root/circt/tools/circt-verilog/circt-verilog.cpp:534:15
#44 0x00007f30dec601ca __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:74:3
#45 0x00007f30dec6028b call_init ./csu/../csu/libc-start.c:128:20
#46 0x00007f30dec6028b __libc_start_main ./csu/../csu/libc-start.c:347:5
#47 0x0000560780aad4d5 _start (/root/circt/build/bin/circt-verilog+0xf94d5)
[1]    1619108 IOT instruction (core dumped)  /root/circt/build/bin/circt-verilog --ir-hw bug.sv

$ circt-verilog --version     
LLVM (http://llvm.org/):
  LLVM version 23.0.0git
  Optimized build with assertions.
CIRCT e4838c703
slang version 9.1.0+0

Root Cause Analysis

The test case violates IEEE 1800 semantics by having multiple drivers to signal q:

• Procedural driver: always @(negedge clk) q <= d
• Continuous driver: assign q = q

The continuous assignment also creates a combinational loop (q depends on itself).

During LLHD lowering, the Sig2Reg pass attempts to promote signals to registers but encounters a circular dependency when processing the self-referencing assignment. This causes infinite recursion in the signal promotion logic.

Cross-Tool Validation

• Icarus Verilog: ✅ Correctly rejects

  error: Cannot perform procedural assignment to variable 'q' because it is also continuously assigned.
  

• Verilator: ✅ Correctly rejects

  %Error-BLKANDNBLK: Blocked and non-blocking assignments to same variable: 'q'
  

• CIRCT: ❌ Hangs indefinitely

Suggested Fix

Add validation in the LLHD lowering pipeline to detect:

1. Multiple drivers to the same signal (procedural + continuous)
2. Combinational loops in signal assignments

The compiler should emit a diagnostic error and fail gracefully instead of hanging.

[5iri]

I think this issue is from Sig2RegPass

I guess we need to bypass Sig2Reg pass when we see llhd.process has 2 llhd.drv on the same variable?

maybe I am over conservative here as there could non-overlapping slices.

[MikePopoloski]

FYI slang will diagnose these if you run its analysis pass after elaboration.

[fabianschuiki]

Nice catch! I suspect the issue here is the assignment assign q = q, which causes some canonicalizer or folder to infinitely loop. Have you tried running your example through circt-verilog --parse-only or circt-verilog --ir-moore to see at which IR stage it hangs? You may also want to run circt-verilog --mlir-print-ir-before-all, which will show you the IR before each transformation pass. I suspect this gets stuck either in a canonicalizer pass, or as @5iri suggested in something like Sig2Reg. If we have the exact MLIR input and the pass that then gets stuck, we'll be able to cook up a smaller test case and fix. The fix is probably to make sure that we break these loops in the IR.

[fabianschuiki]

And we should definitely run the Slang analysis pass that @MikePopoloski suggested. That would make for a nicer user experience 😁

[m2kar]

Nice catch! I suspect the issue here is the assignment assign q = q, which causes some canonicalizer or folder to infinitely loop. Have you tried running your example through circt-verilog --parse-only or circt-verilog --ir-moore to see at which IR stage it hangs? You may also want to run circt-verilog --mlir-print-ir-before-all, which will show you the IR before each transformation pass. I suspect this gets stuck either in a canonicalizer pass, or as @5iri suggested in something like Sig2Reg. If we have the exact MLIR input and the pass that then gets stuck, we'll be able to cook up a smaller test case and fix. The fix is probably to make sure that we break these loops in the IR.

Result of `--parse-only` `--ir-moore` :

$ circt-verilog --parse-only bug.sv 
module {
  moore.module @bug(in %clk : !moore.l1, out q : !moore.l1) {
    %clk_0 = moore.variable name "clk" : <l1>
    %q = moore.variable : <l1>
    %d = moore.variable : <l1>
    moore.procedure always {
      moore.wait_event {
        %3 = moore.read %clk_0 : <l1>
        moore.detect_event negedge %3 : l1
      }
      %2 = moore.read %d : <l1>
      moore.nonblocking_assign %q, %2 : l1
      moore.return
    }
    %0 = moore.read %q : <l1>
    moore.assign %q, %0 : l1
    moore.assign %clk_0, %clk : l1
    %1 = moore.read %q : <l1>
    moore.output %1 : !moore.l1
  }
}

$ circt-verilog --ir-moore bug.sv  
module {
  moore.module @bug(in %clk : !moore.l1, out q : !moore.l1) {
    %clk_0 = moore.variable name "clk" : <l1>
    %q = moore.variable : <l1>
    %d = moore.variable : <l1>
    moore.procedure always {
      moore.wait_event {
        %3 = moore.read %clk_0 : <l1>
        moore.detect_event negedge %3 : l1
      }
      %2 = moore.read %d : <l1>
      moore.nonblocking_assign %q, %2 : l1
      moore.return
    }
    %0 = moore.read %q : <l1>
    moore.assign %q, %0 : l1
    moore.assign %clk_0, %clk : l1
    %1 = moore.read %q : <l1>
    moore.output %1 : !moore.l1
  }
}

And `--mlir-print-ir-before-all`: (Compiler hangs indefinitely ...)

 $ circt-verilog --mlir-print-ir-before-all --ir-hw bug.sv
// -----// IR Dump Before CSE (cse) //----- //
moore.module @bug(in %clk : !moore.l1, out q : !moore.l1) {
  %clk_0 = moore.variable name "clk" : <l1>
  %q = moore.variable : <l1>
  %d = moore.variable : <l1>
  moore.procedure always {
    moore.wait_event {
      %3 = moore.read %clk_0 : <l1>
      moore.detect_event negedge %3 : l1
    }
    %2 = moore.read %d : <l1>
    moore.nonblocking_assign %q, %2 : l1
    moore.return
  }
  %0 = moore.read %q : <l1>
  moore.assign %q, %0 : l1
  moore.assign %clk_0, %clk : l1
  %1 = moore.read %q : <l1>
  moore.output %1 : !moore.l1
}

// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
moore.module @bug(in %clk : !moore.l1, out q : !moore.l1) {
  %clk_0 = moore.variable name "clk" : <l1>
  %q = moore.variable : <l1>
  %d = moore.variable : <l1>
  moore.procedure always {
    moore.wait_event {
      %3 = moore.read %clk_0 : <l1>
      moore.detect_event negedge %3 : l1
    }
    %2 = moore.read %d : <l1>
    moore.nonblocking_assign %q, %2 : l1
    moore.return
  }
  %0 = moore.read %q : <l1>
  moore.assign %q, %0 : l1
  moore.assign %clk_0, %clk : l1
  %1 = moore.read %q : <l1>
  moore.output %1 : !moore.l1
}

// -----// IR Dump Before CreateVTables (moore-create-vtables) //----- //
module {
  moore.module @bug(in %clk : !moore.l1, out q : !moore.l1) {
    %clk_0 = moore.variable name "clk" : <l1>
    %q = moore.variable : <l1>
    %d = moore.variable : <l1>
    moore.procedure always {
      moore.wait_event {
        %3 = moore.read %clk_0 : <l1>
        moore.detect_event negedge %3 : l1
      }
      %2 = moore.read %d : <l1>
      moore.nonblocking_assign %q, %2 : l1
      moore.return
    }
    %0 = moore.read %q : <l1>
    moore.assign %q, %0 : l1
    moore.assign %clk_0, %clk : l1
    %1 = moore.read %q : <l1>
    moore.output %1 : !moore.l1
  }
}


// -----// IR Dump Before SymbolDCE (symbol-dce) //----- //
module {
  moore.module @bug(in %clk : !moore.l1, out q : !moore.l1) {
    %clk_0 = moore.variable name "clk" : <l1>
    %q = moore.variable : <l1>
    %d = moore.variable : <l1>
    moore.procedure always {
      moore.wait_event {
        %3 = moore.read %clk_0 : <l1>
        moore.detect_event negedge %3 : l1
      }
      %2 = moore.read %d : <l1>
      moore.nonblocking_assign %q, %2 : l1
      moore.return
    }
    %0 = moore.read %q : <l1>
    moore.assign %q, %0 : l1
    moore.assign %clk_0, %clk : l1
    %1 = moore.read %q : <l1>
    moore.output %1 : !moore.l1
  }
}


// -----// IR Dump Before LowerConcatRef (moore-lower-concatref) //----- //
moore.module @bug(in %clk : !moore.l1, out q : !moore.l1) {
  %clk_0 = moore.variable name "clk" : <l1>
  %q = moore.variable : <l1>
  %d = moore.variable : <l1>
  moore.procedure always {
    moore.wait_event {
      %3 = moore.read %clk_0 : <l1>
      moore.detect_event negedge %3 : l1
    }
    %2 = moore.read %d : <l1>
    moore.nonblocking_assign %q, %2 : l1
    moore.return
  }
  %0 = moore.read %q : <l1>
  moore.assign %q, %0 : l1
  moore.assign %clk_0, %clk : l1
  %1 = moore.read %q : <l1>
  moore.output %1 : !moore.l1
}

// -----// IR Dump Before SROA (sroa) //----- //
moore.module @bug(in %clk : !moore.l1, out q : !moore.l1) {
  %clk_0 = moore.variable name "clk" : <l1>
  %q = moore.variable : <l1>
  %d = moore.variable : <l1>
  moore.procedure always {
    moore.wait_event {
      %3 = moore.read %clk_0 : <l1>
      moore.detect_event negedge %3 : l1
    }
    %2 = moore.read %d : <l1>
    moore.nonblocking_assign %q, %2 : l1
    moore.return
  }
  %0 = moore.read %q : <l1>
  moore.assign %q, %0 : l1
  moore.assign %clk_0, %clk : l1
  %1 = moore.read %q : <l1>
  moore.output %1 : !moore.l1
}

// -----// IR Dump Before Mem2Reg (mem2reg) //----- //
moore.module @bug(in %clk : !moore.l1, out q : !moore.l1) {
  %clk_0 = moore.variable name "clk" : <l1>
  %q = moore.variable : <l1>
  %d = moore.variable : <l1>
  moore.procedure always {
    moore.wait_event {
      %3 = moore.read %clk_0 : <l1>
      moore.detect_event negedge %3 : l1
    }
    %2 = moore.read %d : <l1>
    moore.nonblocking_assign %q, %2 : l1
    moore.return
  }
  %0 = moore.read %q : <l1>
  moore.assign %q, %0 : l1
  moore.assign %clk_0, %clk : l1
  %1 = moore.read %q : <l1>
  moore.output %1 : !moore.l1
}

// -----// IR Dump Before CSE (cse) //----- //
moore.module @bug(in %clk : !moore.l1, out q : !moore.l1) {
  %clk_0 = moore.variable name "clk" : <l1>
  %q = moore.variable : <l1>
  %d = moore.variable : <l1>
  moore.procedure always {
    moore.wait_event {
      %3 = moore.read %clk_0 : <l1>
      moore.detect_event negedge %3 : l1
    }
    %2 = moore.read %d : <l1>
    moore.nonblocking_assign %q, %2 : l1
    moore.return
  }
  %0 = moore.read %q : <l1>
  moore.assign %q, %0 : l1
  moore.assign %clk_0, %clk : l1
  %1 = moore.read %q : <l1>
  moore.output %1 : !moore.l1
}

// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
moore.module @bug(in %clk : !moore.l1, out q : !moore.l1) {
  %clk_0 = moore.variable name "clk" : <l1>
  %q = moore.variable : <l1>
  %d = moore.variable : <l1>
  moore.procedure always {
    moore.wait_event {
      %3 = moore.read %clk_0 : <l1>
      moore.detect_event negedge %3 : l1
    }
    %2 = moore.read %d : <l1>
    moore.nonblocking_assign %q, %2 : l1
    moore.return
  }
  %0 = moore.read %q : <l1>
  moore.assign %q, %0 : l1
  moore.assign %clk_0, %clk : l1
  %1 = moore.read %q : <l1>
  moore.output %1 : !moore.l1
}

// -----// IR Dump Before ConvertMooreToCore (convert-moore-to-core) //----- //
module {
  moore.module @bug(in %clk : !moore.l1, out q : !moore.l1) {
    %clk_0 = moore.variable name "clk" : <l1>
    %q = moore.variable : <l1>
    %d = moore.variable : <l1>
    moore.procedure always {
      moore.wait_event {
        %3 = moore.read %clk_0 : <l1>
        moore.detect_event negedge %3 : l1
      }
      %2 = moore.read %d : <l1>
      moore.nonblocking_assign %q, %2 : l1
      moore.return
    }
    %0 = moore.read %q : <l1>
    moore.assign %q, %0 : l1
    moore.assign %clk_0, %clk : l1
    %1 = moore.read %q : <l1>
    moore.output %1 : !moore.l1
  }
}


// -----// IR Dump Before CSE (cse) //----- //
hw.module @bug(in %clk : i1, out q : i1) {
  %false = hw.constant false
  %clk_0 = llhd.sig name "clk" %false : i1
  %0 = llhd.prb %clk_0 : i1
  %false_1 = hw.constant false
  %q = llhd.sig %false_1 : i1
  %false_2 = hw.constant false
  %d = llhd.sig %false_2 : i1
  llhd.process {
    cf.br ^bb1
  ^bb1:  // 2 preds: ^bb0, ^bb4
    cf.br ^bb2
  ^bb2:  // 2 preds: ^bb1, ^bb3
    %5 = llhd.prb %clk_0 : i1
    llhd.wait (%0 : i1), ^bb3
  ^bb3:  // pred: ^bb2
    %6 = llhd.prb %clk_0 : i1
    %true = hw.constant true
    %7 = comb.xor bin %6, %true : i1
    %8 = comb.and bin %5, %7 : i1
    cf.cond_br %8, ^bb4, ^bb2
  ^bb4:  // pred: ^bb3
    %9 = llhd.prb %d : i1
    %10 = llhd.constant_time <0ns, 1d, 0e>
    llhd.drv %q, %9 after %10 : i1
    cf.br ^bb1
  }
  %1 = llhd.prb %q : i1
  %2 = llhd.constant_time <0ns, 0d, 1e>
  llhd.drv %q, %1 after %2 : i1
  %3 = llhd.constant_time <0ns, 0d, 1e>
  llhd.drv %clk_0, %clk after %3 : i1
  %4 = llhd.prb %q : i1
  hw.output %4 : i1
}

// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
hw.module @bug(in %clk : i1, out q : i1) {
  %false = hw.constant false
  %clk_0 = llhd.sig name "clk" %false : i1
  %0 = llhd.prb %clk_0 : i1
  %q = llhd.sig %false : i1
  %d = llhd.sig %false : i1
  llhd.process {
    cf.br ^bb1
  ^bb1:  // 2 preds: ^bb0, ^bb4
    cf.br ^bb2
  ^bb2:  // 2 preds: ^bb1, ^bb3
    %3 = llhd.prb %clk_0 : i1
    llhd.wait (%0 : i1), ^bb3
  ^bb3:  // pred: ^bb2
    %4 = llhd.prb %clk_0 : i1
    %true = hw.constant true
    %5 = comb.xor bin %4, %true : i1
    %6 = comb.and bin %3, %5 : i1
    cf.cond_br %6, ^bb4, ^bb2
  ^bb4:  // pred: ^bb3
    %7 = llhd.prb %d : i1
    %8 = llhd.constant_time <0ns, 1d, 0e>
    llhd.drv %q, %7 after %8 : i1
    cf.br ^bb1
  }
  %1 = llhd.prb %q : i1
  %2 = llhd.constant_time <0ns, 0d, 1e>
  llhd.drv %q, %1 after %2 : i1
  llhd.drv %clk_0, %clk after %2 : i1
  hw.output %1 : i1
}

// -----// IR Dump Before WrapProceduralOpsPass (llhd-wrap-procedural-ops) //----- //
hw.module @bug(in %clk : i1, out q : i1) {
  %0 = llhd.constant_time <0ns, 0d, 1e>
  %1 = llhd.constant_time <0ns, 1d, 0e>
  %true = hw.constant true
  %false = hw.constant false
  %clk_0 = llhd.sig name "clk" %false : i1
  %2 = llhd.prb %clk_0 : i1
  %q = llhd.sig %false : i1
  %d = llhd.sig %false : i1
  llhd.process {
    cf.br ^bb1
  ^bb1:  // 3 preds: ^bb0, ^bb2, ^bb3
    %4 = llhd.prb %clk_0 : i1
    llhd.wait (%2 : i1), ^bb2
  ^bb2:  // pred: ^bb1
    %5 = llhd.prb %clk_0 : i1
    %6 = comb.xor bin %5, %true : i1
    %7 = comb.and bin %4, %6 : i1
    cf.cond_br %7, ^bb3, ^bb1
  ^bb3:  // pred: ^bb2
    %8 = llhd.prb %d : i1
    llhd.drv %q, %8 after %1 : i1
    cf.br ^bb1
  }
  %3 = llhd.prb %q : i1
  llhd.drv %q, %3 after %0 : i1
  llhd.drv %clk_0, %clk after %0 : i1
  hw.output %3 : i1
}

// -----// IR Dump Before SCFToControlFlowPass (convert-scf-to-cf) //----- //
module {
  hw.module @bug(in %clk : i1, out q : i1) {
    %0 = llhd.constant_time <0ns, 0d, 1e>
    %1 = llhd.constant_time <0ns, 1d, 0e>
    %true = hw.constant true
    %false = hw.constant false
    %clk_0 = llhd.sig name "clk" %false : i1
    %2 = llhd.prb %clk_0 : i1
    %q = llhd.sig %false : i1
    %d = llhd.sig %false : i1
    llhd.process {
      cf.br ^bb1
    ^bb1:  // 3 preds: ^bb0, ^bb2, ^bb3
      %4 = llhd.prb %clk_0 : i1
      llhd.wait (%2 : i1), ^bb2
    ^bb2:  // pred: ^bb1
      %5 = llhd.prb %clk_0 : i1
      %6 = comb.xor bin %5, %true : i1
      %7 = comb.and bin %4, %6 : i1
      cf.cond_br %7, ^bb3, ^bb1
    ^bb3:  // pred: ^bb2
      %8 = llhd.prb %d : i1
      llhd.drv %q, %8 after %1 : i1
      cf.br ^bb1
    }
    %3 = llhd.prb %q : i1
    llhd.drv %q, %3 after %0 : i1
    llhd.drv %clk_0, %clk after %0 : i1
    hw.output %3 : i1
  }
}


// -----// IR Dump Before InlineCallsPass (llhd-inline-calls) //----- //
module {
  hw.module @bug(in %clk : i1, out q : i1) {
    %0 = llhd.constant_time <0ns, 0d, 1e>
    %1 = llhd.constant_time <0ns, 1d, 0e>
    %true = hw.constant true
    %false = hw.constant false
    %clk_0 = llhd.sig name "clk" %false : i1
    %2 = llhd.prb %clk_0 : i1
    %q = llhd.sig %false : i1
    %d = llhd.sig %false : i1
    llhd.process {
      cf.br ^bb1
    ^bb1:  // 3 preds: ^bb0, ^bb2, ^bb3
      %4 = llhd.prb %clk_0 : i1
      llhd.wait (%2 : i1), ^bb2
    ^bb2:  // pred: ^bb1
      %5 = llhd.prb %clk_0 : i1
      %6 = comb.xor bin %5, %true : i1
      %7 = comb.and bin %4, %6 : i1
      cf.cond_br %7, ^bb3, ^bb1
    ^bb3:  // pred: ^bb2
      %8 = llhd.prb %d : i1
      llhd.drv %q, %8 after %1 : i1
      cf.br ^bb1
    }
    %3 = llhd.prb %q : i1
    llhd.drv %q, %3 after %0 : i1
    llhd.drv %clk_0, %clk after %0 : i1
    hw.output %3 : i1
  }
}


// -----// IR Dump Before SymbolDCE (symbol-dce) //----- //
module {
  hw.module @bug(in %clk : i1, out q : i1) {
    %0 = llhd.constant_time <0ns, 0d, 1e>
    %1 = llhd.constant_time <0ns, 1d, 0e>
    %true = hw.constant true
    %false = hw.constant false
    %clk_0 = llhd.sig name "clk" %false : i1
    %2 = llhd.prb %clk_0 : i1
    %q = llhd.sig %false : i1
    %d = llhd.sig %false : i1
    llhd.process {
      cf.br ^bb1
    ^bb1:  // 3 preds: ^bb0, ^bb2, ^bb3
      %4 = llhd.prb %clk_0 : i1
      llhd.wait (%2 : i1), ^bb2
    ^bb2:  // pred: ^bb1
      %5 = llhd.prb %clk_0 : i1
      %6 = comb.xor bin %5, %true : i1
      %7 = comb.and bin %4, %6 : i1
      cf.cond_br %7, ^bb3, ^bb1
    ^bb3:  // pred: ^bb2
      %8 = llhd.prb %d : i1
      llhd.drv %q, %8 after %1 : i1
      cf.br ^bb1
    }
    %3 = llhd.prb %q : i1
    llhd.drv %q, %3 after %0 : i1
    llhd.drv %clk_0, %clk after %0 : i1
    hw.output %3 : i1
  }
}


// -----// IR Dump Before Mem2RegPass (llhd-mem2reg) //----- //
hw.module @bug(in %clk : i1, out q : i1) {
  %0 = llhd.constant_time <0ns, 0d, 1e>
  %1 = llhd.constant_time <0ns, 1d, 0e>
  %true = hw.constant true
  %false = hw.constant false
  %clk_0 = llhd.sig name "clk" %false : i1
  %2 = llhd.prb %clk_0 : i1
  %q = llhd.sig %false : i1
  %d = llhd.sig %false : i1
  llhd.process {
    cf.br ^bb1
  ^bb1:  // 3 preds: ^bb0, ^bb2, ^bb3
    %4 = llhd.prb %clk_0 : i1
    llhd.wait (%2 : i1), ^bb2
  ^bb2:  // pred: ^bb1
    %5 = llhd.prb %clk_0 : i1
    %6 = comb.xor bin %5, %true : i1
    %7 = comb.and bin %4, %6 : i1
    cf.cond_br %7, ^bb3, ^bb1
  ^bb3:  // pred: ^bb2
    %8 = llhd.prb %d : i1
    llhd.drv %q, %8 after %1 : i1
    cf.br ^bb1
  }
  %3 = llhd.prb %q : i1
  llhd.drv %q, %3 after %0 : i1
  llhd.drv %clk_0, %clk after %0 : i1
  hw.output %3 : i1
}

// -----// IR Dump Before HoistSignalsPass (llhd-hoist-signals) //----- //
hw.module @bug(in %clk : i1, out q : i1) {
  %0 = llhd.constant_time <0ns, 0d, 1e>
  %true = hw.constant true
  %false = hw.constant false
  %clk_0 = llhd.sig name "clk" %false : i1
  %1 = llhd.prb %clk_0 : i1
  %q = llhd.sig %false : i1
  %d = llhd.sig %false : i1
  llhd.process {
    %3 = llhd.prb %clk_0 : i1
    %false_1 = hw.constant false
    %false_2 = hw.constant false
    cf.br ^bb1(%3, %false_1, %false_2 : i1, i1, i1)
  ^bb1(%4: i1, %5: i1, %6: i1):  // 3 preds: ^bb0, ^bb2, ^bb3
    %7 = llhd.constant_time <0ns, 1d, 0e>
    llhd.drv %q, %5 after %7 if %6 : i1
    llhd.wait (%1 : i1), ^bb2(%4 : i1)
  ^bb2(%8: i1):  // pred: ^bb1
    %9 = llhd.prb %clk_0 : i1
    %10 = llhd.prb %d : i1
    %11 = comb.xor bin %9, %true : i1
    %12 = comb.and bin %8, %11 : i1
    %false_3 = hw.constant false
    %false_4 = hw.constant false
    cf.cond_br %12, ^bb3, ^bb1(%9, %false_3, %false_4 : i1, i1, i1)
  ^bb3:  // pred: ^bb2
    %true_5 = hw.constant true
    cf.br ^bb1(%9, %10, %true_5 : i1, i1, i1)
  }
  %2 = llhd.prb %q : i1
  llhd.drv %q, %2 after %0 : i1
  llhd.drv %clk_0, %clk after %0 : i1
  hw.output %2 : i1
}

// -----// IR Dump Before DeseqPass (llhd-deseq) //----- //
hw.module @bug(in %clk : i1, out q : i1) {
  %0 = llhd.constant_time <0ns, 0d, 1e>
  %true = hw.constant true
  %false = hw.constant false
  %clk_0 = llhd.sig name "clk" %false : i1
  %1 = llhd.prb %clk_0 : i1
  %q = llhd.sig %false : i1
  %d = llhd.sig %false : i1
  %2 = llhd.prb %d : i1
  %3 = llhd.constant_time <0ns, 1d, 0e>
  %4:2 = llhd.process -> i1, i1 {
    %false_1 = hw.constant false
    %false_2 = hw.constant false
    cf.br ^bb1(%1, %false_1, %false_2 : i1, i1, i1)
  ^bb1(%6: i1, %7: i1, %8: i1):  // 3 preds: ^bb0, ^bb2, ^bb3
    llhd.wait yield (%7, %8 : i1, i1), (%1 : i1), ^bb2(%6 : i1)
  ^bb2(%9: i1):  // pred: ^bb1
    %10 = comb.xor bin %1, %true : i1
    %11 = comb.and bin %9, %10 : i1
    %false_3 = hw.constant false
    %false_4 = hw.constant false
    cf.cond_br %11, ^bb3, ^bb1(%1, %false_3, %false_4 : i1, i1, i1)
  ^bb3:  // pred: ^bb2
    %true_5 = hw.constant true
    cf.br ^bb1(%1, %2, %true_5 : i1, i1, i1)
  }
  llhd.drv %q, %4#0 after %3 if %4#1 : i1
  %5 = llhd.prb %q : i1
  llhd.drv %q, %5 after %0 : i1
  llhd.drv %clk_0, %clk after %0 : i1
  hw.output %5 : i1
}

// -----// IR Dump Before LowerProcessesPass (llhd-lower-processes) //----- //
hw.module @bug(in %clk : i1, out q : i1) {
  %0 = llhd.constant_time <0ns, 0d, 1e>
  %true = hw.constant true
  %false = hw.constant false
  %clk_0 = llhd.sig name "clk" %false : i1
  %1 = llhd.prb %clk_0 : i1
  %q = llhd.sig %false : i1
  %d = llhd.sig %false : i1
  %2 = llhd.prb %d : i1
  %3 = llhd.constant_time <0ns, 1d, 0e>
  %4 = seq.to_clock %1
  %5 = seq.clock_inv %4
  %q_1 = seq.firreg %2 clock %5 {name = "q"} : i1
  %6 = llhd.constant_time <0ns, 0d, 1e>
  llhd.drv %q, %q_1 after %6 : i1
  %7 = llhd.prb %q : i1
  llhd.drv %q, %7 after %0 : i1
  llhd.drv %clk_0, %clk after %0 : i1
  hw.output %7 : i1
}

// -----// IR Dump Before CSE (cse) //----- //
hw.module @bug(in %clk : i1, out q : i1) {
  %0 = llhd.constant_time <0ns, 0d, 1e>
  %true = hw.constant true
  %false = hw.constant false
  %clk_0 = llhd.sig name "clk" %false : i1
  %1 = llhd.prb %clk_0 : i1
  %q = llhd.sig %false : i1
  %d = llhd.sig %false : i1
  %2 = llhd.prb %d : i1
  %3 = llhd.constant_time <0ns, 1d, 0e>
  %4 = seq.to_clock %1
  %5 = seq.clock_inv %4
  %q_1 = seq.firreg %2 clock %5 {name = "q"} : i1
  %6 = llhd.constant_time <0ns, 0d, 1e>
  llhd.drv %q, %q_1 after %6 : i1
  %7 = llhd.prb %q : i1
  llhd.drv %q, %7 after %0 : i1
  llhd.drv %clk_0, %clk after %0 : i1
  hw.output %7 : i1
}

// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
hw.module @bug(in %clk : i1, out q : i1) {
  %0 = llhd.constant_time <0ns, 0d, 1e>
  %false = hw.constant false
  %clk_0 = llhd.sig name "clk" %false : i1
  %1 = llhd.prb %clk_0 : i1
  %q = llhd.sig %false : i1
  %d = llhd.sig %false : i1
  %2 = llhd.prb %d : i1
  %3 = seq.to_clock %1
  %4 = seq.clock_inv %3
  %q_1 = seq.firreg %2 clock %4 {name = "q"} : i1
  llhd.drv %q, %q_1 after %0 : i1
  %5 = llhd.prb %q : i1
  llhd.drv %q, %5 after %0 : i1
  llhd.drv %clk_0, %clk after %0 : i1
  hw.output %5 : i1
}

// -----// IR Dump Before UnrollLoopsPass (llhd-unroll-loops) //----- //
hw.module @bug(in %clk : i1, out q : i1) {
  %0 = llhd.constant_time <0ns, 0d, 1e>
  %false = hw.constant false
  %clk_0 = llhd.sig name "clk" %false : i1
  %1 = llhd.prb %clk_0 : i1
  %q = llhd.sig %false : i1
  %d = llhd.sig %false : i1
  %2 = llhd.prb %d : i1
  %3 = seq.to_clock %1
  %4 = seq.clock_inv %3
  %q_1 = seq.firreg %2 clock %4 {name = "q"} : i1
  llhd.drv %q, %q_1 after %0 : i1
  %5 = llhd.prb %q : i1
  llhd.drv %q, %5 after %0 : i1
  llhd.drv %clk_0, %clk after %0 : i1
  hw.output %5 : i1
}

// -----// IR Dump Before CSE (cse) //----- //
hw.module @bug(in %clk : i1, out q : i1) {
  %0 = llhd.constant_time <0ns, 0d, 1e>
  %false = hw.constant false
  %clk_0 = llhd.sig name "clk" %false : i1
  %1 = llhd.prb %clk_0 : i1
  %q = llhd.sig %false : i1
  %d = llhd.sig %false : i1
  %2 = llhd.prb %d : i1
  %3 = seq.to_clock %1
  %4 = seq.clock_inv %3
  %q_1 = seq.firreg %2 clock %4 {name = "q"} : i1
  llhd.drv %q, %q_1 after %0 : i1
  %5 = llhd.prb %q : i1
  llhd.drv %q, %5 after %0 : i1
  llhd.drv %clk_0, %clk after %0 : i1
  hw.output %5 : i1
}

// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
hw.module @bug(in %clk : i1, out q : i1) {
  %0 = llhd.constant_time <0ns, 0d, 1e>
  %false = hw.constant false
  %clk_0 = llhd.sig name "clk" %false : i1
  %1 = llhd.prb %clk_0 : i1
  %q = llhd.sig %false : i1
  %d = llhd.sig %false : i1
  %2 = llhd.prb %d : i1
  %3 = seq.to_clock %1
  %4 = seq.clock_inv %3
  %q_1 = seq.firreg %2 clock %4 {name = "q"} : i1
  llhd.drv %q, %q_1 after %0 : i1
  %5 = llhd.prb %q : i1
  llhd.drv %q, %5 after %0 : i1
  llhd.drv %clk_0, %clk after %0 : i1
  hw.output %5 : i1
}

// -----// IR Dump Before RemoveControlFlowPass (llhd-remove-control-flow) //----- //
hw.module @bug(in %clk : i1, out q : i1) {
  %0 = llhd.constant_time <0ns, 0d, 1e>
  %false = hw.constant false
  %clk_0 = llhd.sig name "clk" %false : i1
  %1 = llhd.prb %clk_0 : i1
  %q = llhd.sig %false : i1
  %d = llhd.sig %false : i1
  %2 = llhd.prb %d : i1
  %3 = seq.to_clock %1
  %4 = seq.clock_inv %3
  %q_1 = seq.firreg %2 clock %4 {name = "q"} : i1
  llhd.drv %q, %q_1 after %0 : i1
  %5 = llhd.prb %q : i1
  llhd.drv %q, %5 after %0 : i1
  llhd.drv %clk_0, %clk after %0 : i1
  hw.output %5 : i1
}

// -----// IR Dump Before CSE (cse) //----- //
hw.module @bug(in %clk : i1, out q : i1) {
  %0 = llhd.constant_time <0ns, 0d, 1e>
  %false = hw.constant false
  %clk_0 = llhd.sig name "clk" %false : i1
  %1 = llhd.prb %clk_0 : i1
  %q = llhd.sig %false : i1
  %d = llhd.sig %false : i1
  %2 = llhd.prb %d : i1
  %3 = seq.to_clock %1
  %4 = seq.clock_inv %3
  %q_1 = seq.firreg %2 clock %4 {name = "q"} : i1
  llhd.drv %q, %q_1 after %0 : i1
  %5 = llhd.prb %q : i1
  llhd.drv %q, %5 after %0 : i1
  llhd.drv %clk_0, %clk after %0 : i1
  hw.output %5 : i1
}

// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
hw.module @bug(in %clk : i1, out q : i1) {
  %0 = llhd.constant_time <0ns, 0d, 1e>
  %false = hw.constant false
  %clk_0 = llhd.sig name "clk" %false : i1
  %1 = llhd.prb %clk_0 : i1
  %q = llhd.sig %false : i1
  %d = llhd.sig %false : i1
  %2 = llhd.prb %d : i1
  %3 = seq.to_clock %1
  %4 = seq.clock_inv %3
  %q_1 = seq.firreg %2 clock %4 {name = "q"} : i1
  llhd.drv %q, %q_1 after %0 : i1
  %5 = llhd.prb %q : i1
  llhd.drv %q, %5 after %0 : i1
  llhd.drv %clk_0, %clk after %0 : i1
  hw.output %5 : i1
}

// -----// IR Dump Before MapArithToCombPass (map-arith-to-comb) //----- //
hw.module @bug(in %clk : i1, out q : i1) {
  %0 = llhd.constant_time <0ns, 0d, 1e>
  %false = hw.constant false
  %clk_0 = llhd.sig name "clk" %false : i1
  %1 = llhd.prb %clk_0 : i1
  %q = llhd.sig %false : i1
  %d = llhd.sig %false : i1
  %2 = llhd.prb %d : i1
  %3 = seq.to_clock %1
  %4 = seq.clock_inv %3
  %q_1 = seq.firreg %2 clock %4 {name = "q"} : i1
  llhd.drv %q, %q_1 after %0 : i1
  %5 = llhd.prb %q : i1
  llhd.drv %q, %5 after %0 : i1
  llhd.drv %clk_0, %clk after %0 : i1
  hw.output %5 : i1
}

// -----// IR Dump Before CombineDrivesPass (llhd-combine-drives) //----- //
hw.module @bug(in %clk : i1, out q : i1) {
  %0 = llhd.constant_time <0ns, 0d, 1e>
  %false = hw.constant false
  %clk_0 = llhd.sig name "clk" %false : i1
  %1 = llhd.prb %clk_0 : i1
  %q = llhd.sig %false : i1
  %d = llhd.sig %false : i1
  %2 = llhd.prb %d : i1
  %3 = seq.to_clock %1
  %4 = seq.clock_inv %3
  %q_1 = seq.firreg %2 clock %4 {name = "q"} : i1
  llhd.drv %q, %q_1 after %0 : i1
  %5 = llhd.prb %q : i1
  llhd.drv %q, %5 after %0 : i1
  llhd.drv %clk_0, %clk after %0 : i1
  hw.output %5 : i1
}

// -----// IR Dump Before Sig2Reg (llhd-sig2reg) //----- //
hw.module @bug(in %clk : i1, out q : i1) {
  %0 = llhd.constant_time <0ns, 0d, 1e>
  %false = hw.constant false
  %clk_0 = llhd.sig name "clk" %false : i1
  %1 = llhd.prb %clk_0 : i1
  %q = llhd.sig %false : i1
  %d = llhd.sig %false : i1
  %2 = llhd.prb %d : i1
  %3 = seq.to_clock %1
  %4 = seq.clock_inv %3
  %q_1 = seq.firreg %2 clock %4 {name = "q"} : i1
  llhd.drv %q, %q_1 after %0 : i1
  %5 = llhd.prb %q : i1
  llhd.drv %q, %5 after %0 : i1
  llhd.drv %clk_0, %clk after %0 : i1
  hw.output %5 : i1
}

(Compiler hangs indefinitely ... )

[fabianschuiki]

Nice, thanks for running the commands again @m2kar! Looks like @5iri was right: this hangs in the Sig2Reg pass. That pass probably collects a list of values driven onto a signal, and also values driven onto a signal through projections. The code that collects this list is probably getting stuck in an infinite loop because of q = q. We should probably add a set of visited ops there to break any recursions and ignore any signals where this occurs. (It's okay to keep signals around after Sig2Reg if they don't have a trivial replacement with a driven value.)