# RTL Mini Projects - Verilog HDL
This repository contains a collection of RTL mini projects developed as part of my learning in digital design and VLSI front-end using Verilog HDL. Each project focuses on building strong foundations in combinational logic, sequential circuits and FSM-based controller design.
-> This repository represents Phase-1 Cycle-1: RTL Coding Foundations of my RTL learning journey, focused on mastering the fundamentals of synthesizable RTL design and verification.
The goal of this repository is to:
- Practice synthesizable RTL coding
- Understand digital design fundamentals
- Build and verify designs using testbenches
- Create a small RTL portfolio for front-end VLSI roles
## Repository Structure
RTL-Coding-Foundations/
├── Week-1/ # Mini ALU (Combinational Logic)
├── Week-2/ # Mod-10 Up/Down Counter
├── Week-3/ # Sequence Detector FSM (1011)
├── Week-4/ # traffic Light Controller FSM
└── README.md
Each folder contains:
- RTL source file
- Testbench
- A dedicated README explaining the design
## Projects Overview
| Week | Project | Key Concepts |
|---|---|---|
| 1 | Mini ALU | Combinational logic, case statements |
| 2 | Mod-10 Up/down Counter | Sequential logic, counters, clock & reset |
| 3 | Sequence Detector FSM (1011) | Moore FSM, overlapping detection |
| 4 | Traffic Light Controller | Timed FSM, controller design |
## Tools & Skills
- Verilog HDL
- RTL Design
- Digital Logic Design
- Sequential Circuits
- Finite State Machines (FSM)
- Testbench Development
- HDL Simulation (ModelSim / EDA Playground)
- Linux & Git
## About Me
I'm an Electronics Engineering student specializing in VLSI Design and Technology, building strong foundations in RTL design and verification for front-end VLSI roles.
# Author: MARK JUSTIN