[RVV] Add support for Ara vector processor

.github/workflows/build.yml

@@ -27,7 +27,6 @@ jobs:
         uses: actions/setup-python@v2
         with:
           python-version: 3.9
-          cache: pip
       -
         name: Install Python requirements
         run: pip install -r requirements.txt

.github/workflows/lint.yml

@@ -82,7 +82,6 @@ jobs:
       uses: actions/setup-python@v2
       with:
         python-version: 3.9
-        cache: pip
     -
       name: Install Python requirements
       run: pip install -r requirements.txt

.github/workflows/publish-docs.yml

@@ -26,7 +26,6 @@ jobs:
         uses: actions/setup-python@v2
         with:
           python-version: 3.9
-          cache: pip
       -
         name: Install Python requirements
         run: pip install -r requirements.txt

Bender.lock

@@ -14,6 +14,17 @@ packages:
     dependencies:
     - apb
     - register_interface
+  ara:
+    revision: 2895ba907e9eb14b3464609dc791a969d159a7c3
+    version: null
+    source:
+      Git: https://github.com/pulp-platform/ara.git
+    dependencies:
+    - apb
+    - axi
+    - common_cells
+    - cva6
+    - tech_cells_generic
   axi:
     revision: 39f5f2d51c5e524f6fc5cf8b6e901f7dcc5622d7
     version: 0.39.6
@@ -99,7 +110,7 @@ packages:
       Git: https://github.com/pulp-platform/common_verification.git
     dependencies: []
   cva6:
-    revision: 9338c2ca7cf1a47aef54322f89ce867825c3c8d5
+    revision: 99eac9a649001bdf5b8f9da52e0ca73d5c48db1c
     version: null
     source:
       Git: https://github.com/pulp-platform/cva6.git
@@ -116,8 +127,8 @@ packages:
     dependencies:
     - axi
   fpnew:
-    revision: f231041c610f270ffc03cbdac38739ddb6426572
-    version: null
+    revision: e5aa6a01b5bbe1675c3aa8872e1203413ded83d1
+    version: 0.2.3
     source:
       Git: https://github.com/pulp-platform/cvfpu.git
     dependencies:

Bender.yml

@@ -22,7 +22,8 @@ dependencies:
   clint:                    { git: "https://github.com/pulp-platform/clint.git",                  version: 0.2.0  }
   common_cells:             { git: "https://github.com/pulp-platform/common_cells.git",           version: 1.33.0 }
   common_verification:      { git: "https://github.com/pulp-platform/common_verification.git",    version: 0.2.0  }
-  cva6:                     { git: "https://github.com/pulp-platform/cva6.git",                   rev: pulp-v1.0.0 }
+  cva6:                     { git: "https://github.com/pulp-platform/cva6.git",                   rev: pulp-v2.0.0-alpha.1 }
+  ara:                      { git: "https://github.com/pulp-platform/ara.git",                    rev: 2895ba907e9eb14b3464609dc791a969d159a7c3 } # mp/cheshire-integration-fix
   iDMA:                     { git: "https://github.com/pulp-platform/iDMA.git",                   version: 0.6.3  }
   irq_router:               { git: "https://github.com/pulp-platform/irq_router.git",             version: 0.0.1-beta.1 }
   opentitan_peripherals:    { git: "https://github.com/pulp-platform/opentitan_peripherals.git",  version: 0.4.0  }

cheshire.mk

@@ -16,7 +16,7 @@ VLOG_ARGS   ?= -suppress 2583 -suppress 13314 -timescale 1ns/1ps
 VLOGAN_ARGS ?= -kdb -nc -assert svaext +v2k -timescale=1ns/1ps
 
 # Common Bender flags for Cheshire RTL
-CHS_BENDER_RTL_FLAGS ?= -t rtl -t cva6 -t cv64a6_imafdcsclic_sv39
+CHS_BENDER_RTL_FLAGS ?= -t rtl -t cva6 -t cv64a6_imafdchsclic_sv39_wb
 
 # Define used paths (prefixed to avoid name conflicts)
 CHS_ROOT      ?= $(shell $(BENDER) path cheshire)
@@ -63,7 +63,7 @@ chs-clean-deps:
 ######################
 
 CHS_NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:pulp-restricted/cheshire-nonfree.git
-CHS_NONFREE_COMMIT ?= 99aa8d9
+CHS_NONFREE_COMMIT ?= 5eb95050b2c043250d717046939ac78f24845d56
 
 CHS_PHONY += chs-nonfree-init
 chs-nonfree-init:

hw/cheshire_pkg.sv

@@ -138,6 +138,7 @@ package cheshire_pkg;
     bit     Clic;
     bit     IrqRouter;
     bit     BusErr;
+    bit     Ara;
     // Parameters for Debug Module
     jtag_idcode_t DbgIdCode;
     dw_bt   DbgMaxReqs;
@@ -196,6 +197,9 @@ package cheshire_pkg;
     aw_bt   AxiRtNumAddrRegions;
     bit     AxiRtCutPaths;
     bit     AxiRtEnableChecks;
+    // Parameters for Ara
+    byte_bt AraNrLanes;
+    word_bt AraVLEN;
   } cheshire_cfg_t;
 
   //////////////////
@@ -295,6 +299,7 @@ package cheshire_pkg;
   typedef struct packed {
     aw_bt [2**MaxCoresWidth-1:0] cores;
     aw_bt dbg;
+    aw_bt ara;
     aw_bt dma;
     aw_bt slink;
     aw_bt vga;
@@ -308,6 +313,7 @@ package cheshire_pkg;
     int unsigned i = 0;
     for (int j = 0; j < cfg.NumCores; j++) begin ret.cores[i] = i; i++; end
     ret.dbg = i;
+    if (cfg.Ara)        begin i++; ret.ara   = i; end
     if (cfg.Dma)        begin i++; ret.dma   = i; end
     if (cfg.SerialLink) begin i++; ret.slink = i; end
     if (cfg.Vga)        begin i++; ret.vga   = i; end
@@ -480,74 +486,44 @@ package cheshire_pkg;
     endcase
   endfunction
 
-  function automatic config_pkg::cva6_cfg_t gen_cva6_cfg(cheshire_cfg_t cfg);
+  function automatic config_pkg::cva6_user_cfg_t gen_cva6_cfg(cheshire_cfg_t cfg);
     doub_bt SizeSpm = get_llc_size(cfg);
     doub_bt SizeLlcOut = cfg.LlcOutRegionEnd - cfg.LlcOutRegionStart;
     doub_bt CieBase   = cfg.Cva6ExtCieOnTop ? 64'h8000_0000 - cfg.Cva6ExtCieLength : 64'h2000_0000;
     doub_bt NoCieBase = cfg.Cva6ExtCieOnTop ? 64'h2000_0000 : 64'h2000_0000 + cfg.Cva6ExtCieLength;
-    return config_pkg::cva6_cfg_t'{
-      NrCommitPorts         : 2,
-      AxiAddrWidth          : cfg.AddrWidth,
-      AxiDataWidth          : cfg.AxiDataWidth,
-      AxiIdWidth            : Cva6IdWidth,
-      AxiUserWidth          : cfg.AxiUserWidth,
-      NrLoadBufEntries      : 2,
-      FpuEn                 : 1,
-      XF16                  : 0,
-      XF16ALT               : 0,
-      XF8                   : 0,
-      XF8ALT                : 0,
-      RVA                   : 1,
-      RVB                   : 0,
-      RVV                   : 0,
-      RVC                   : 1,
-      RVH                   : 1,
-      RVZCB                 : 1,
-      XFVec                 : 0,
-      CvxifEn               : 0,
-      ZiCondExtEn           : 1,
-      RVSCLIC               : cfg.Clic,
-      RVF                   : 1,
-      RVD                   : 1,
-      FpPresent             : 1,
-      NSX                   : 0,
-      FLen                  : 64,
-      RVFVec                : 0,
-      XF16Vec               : 0,
-      XF16ALTVec            : 0,
-      XF8Vec                : 0,
-      NrRgprPorts           : 0,
-      NrWbPorts             : 0,
-      EnableAccelerator     : 0,
-      RVS                   : 1,
-      RVU                   : 1,
-      HaltAddress           : 'h800, // Relative to AmDbg
-      ExceptionAddress      : 'h810, // Relative to AmDbg
-      RASDepth              : cfg.Cva6RASDepth,
-      BTBEntries            : cfg.Cva6BTBEntries,
-      BHTEntries            : cfg.Cva6BHTEntries,
-      DmBaseAddress         : AmDbg,
-      TvalEn                : 1,
-      NrPMPEntries          : cfg.Cva6NrPMPEntries,
-      PMPCfgRstVal          : {16{64'h0}},
-      PMPAddrRstVal         : {16{64'h0}},
-      PMPEntryReadOnly      : 16'd0,
-      NOCType               : config_pkg::NOC_TYPE_AXI4_ATOP,
-      CLICNumInterruptSrc   : NumCoreIrqs + NumIntIntrs + cfg.NumExtClicIntrs,
-      NrNonIdempotentRules  : 2,   // Periphs, ExtNonCIE
-      NonIdempotentAddrBase : {64'h0000_0000, NoCieBase},
-      NonIdempotentLength   : {64'h1000_0000, 64'h6000_0000 - cfg.Cva6ExtCieLength},
-      NrExecuteRegionRules  : 5,   // Debug, Bootrom, AllSPM, LLCOut, ExtCIE
-      ExecuteRegionAddrBase : {AmDbg, AmBrom, AmSpm, cfg.LlcOutRegionStart, CieBase},
-      ExecuteRegionLength   : {64'h40000, 64'h40000, 2*SizeSpm, SizeLlcOut, cfg.Cva6ExtCieLength},
-      NrCachedRegionRules   : 3,   // CachedSPM, LLCOut, ExtCIE
-      CachedRegionAddrBase  : {AmSpm,   cfg.LlcOutRegionStart,  CieBase},
-      CachedRegionLength    : {SizeSpm, SizeLlcOut,             cfg.Cva6ExtCieLength},
-      MaxOutstandingStores  : 7,
-      DebugEn               : 1,
-      NonIdemPotenceEn      : 0,
-      AxiBurstWriteEn       : 0
-    };
+    // Base our config on the upstream default for this variant
+    config_pkg::cva6_user_cfg_t ret = cva6_config_pkg::cva6_cfg;
+    // Modify what we need to
+    ret.AxiAddrWidth          = cfg.AddrWidth;
+    ret.AxiDataWidth          = cfg.AxiDataWidth;
+    ret.AxiIdWidth            = Cva6IdWidth;
+    ret.AxiUserWidth          = cfg.AxiUserWidth;
+    ret.CvxifEn               = 0;
+    ret.DmBaseAddress         = AmDbg;
+    ret.HaltAddress           = 'h800; // Relative to AmDbg
+    ret.ExceptionAddress      = 'h810; // Relative to AmDbg
+    ret.NrNonIdempotentRules  = 2;   // Periphs, ExtNonCI;
+    ret.NonIdempotentAddrBase = {64'h0000_0000, NoCieBase};
+    ret.NOCType               = config_pkg::NOC_TYPE_AXI4_ATOP;
+    ret.NonIdempotentLength   = {64'h1000_0000, 64'h6000_0000 - cfg.Cva6ExtCieLength};
+    ret.NrExecuteRegionRules  = 5;   // Debug, Bootrom, AllSPM, LLCOut, ExtCI;
+    ret.ExecuteRegionAddrBase = {AmDbg, AmBrom, AmSpm, cfg.LlcOutRegionStart, CieBase};
+    ret.ExecuteRegionLength   = {64'h40000, 64'h40000, 2*SizeSpm, SizeLlcOut, cfg.Cva6ExtCieLength};
+    ret.NrCachedRegionRules   = 3;   // CachedSPM, LLCOut, ExtCI;
+    ret.CachedRegionAddrBase  = {AmSpm,   cfg.LlcOutRegionStart,  CieBase};
+    ret.CachedRegionLength    = {SizeSpm, SizeLlcOut,             cfg.Cva6ExtCieLength};
+    ret.DebugEn               = 1;
+    ret.RVSCLIC               = cfg.Clic;
+    ret.CLICNumInterruptSrc   = NumCoreIrqs + NumIntIntrs + cfg.NumExtClicIntrs;
+    // TODO: Should some things be removed from the main config?
+    // TODO: Should other things be added to the main config?
+    // TODO: Tune missing parameters of interest (esp. cache and interconnect) properly
+    ret.RASDepth              = cfg.Cva6RASDepth;
+    ret.BTBEntries            = cfg.Cva6BTBEntries;
+    ret.BHTEntries            = cfg.Cva6BHTEntries;
+    ret.NrPMPEntries          = cfg.Cva6NrPMPEntries;
+    // Return modified config
+    return ret;
   endfunction
 
   ////////////////
@@ -612,6 +588,7 @@ package cheshire_pkg;
     Clic              : 0,
     IrqRouter         : 0,
     BusErr            : 1,
+    Ara               : 0,
     // Debug
     DbgIdCode         : CheshireIdCode,
     DbgMaxReqs        : 4,
@@ -669,6 +646,9 @@ package cheshire_pkg;
     AxiRtWBufferDepth   : 16,
     AxiRtNumAddrRegions : 2,
     AxiRtCutPaths       : 1,
+    // Ara
+    AraNrLanes          : 2,
+    AraVLEN             : 2048,
     // All non-set values should be zero
     default: '0
   };