[core] Add Single-Cycle CSR Dump Mechanism for Debugging

[viv-eth]

Description

This PR introduces a CSR register dump mechanism that allows for single-cycle "printing" of register values instead of raising an exception for unknown CSR accesses. The goal is to enable fast debugging during simulation by directly displaying register contents when a specific CSR is accessed.

Changes

• Introduced CSR Dump Signals:
  • Added csr_dump_read and csr_dump_write to track read and write attempts.
  • Defined a new CSR trigger address (CSR_DUMP_TRIGGER = 12'h7FF) to selectively dump CSR values.
• Modified Exception Handling for Illegal CSR Accesses:
  • Instead of immediately raising an exception, the system now:
    • Detects access to CSR_DUMP_TRIGGER and logs the value.
    • Uses $display to output the register content.
    • Skips raising an exception for this specific CSR, allowing simulation to proceed.
• Implemented a Debug-Only CSR Dump Process:
  • Uses an always block to check if csr_dump is triggered.
  • If csr_dump_write is set, the following message is printed:

    $display("[CSR DUMP] Time: %0t, Core: %0d, Address: 0x%03h, Data: 0x%08h", 
             $time, hart_id_i, conv_csr_addr.address, csr_wdata);

  • Wrapped in pragma translate_off/on to avoid synthesis impact.

Motivation

• Enable Fast Debugging Without UART Overhead:
  • Traditional UART-based debugging (printf via UART) slows down simulation significantly.
  • This method directly prints register values in a single cycle, avoiding communication delays.

TODO

• Implement Buffering for Multi-Value Dumps:
  • Buffer values instead of printing one per cycle until a \n is detected.
  • Enable detection of format delimiters (printf-style) to properly format multi-line outputs.
• Remove trailing comment (around line 2280)