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5 changes: 2 additions & 3 deletions Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -34,9 +34,8 @@ GHDLFLAGS = --workdir=$(OUT_DIR) --ieee=synopsys -fexplicit -frelaxed-rules --w
include $(RUCKUS_DIR)/system_shared.mk

# Override system_shared.mk build string
export BUILD_SVR_TYPE = $(shell python3 -m platform)
export GHDL_VERSION = $(shell ghdl -v 2>&1 | head -n 1)
export BUILD_STRING = $(PROJECT): $(GHDL_VERSION), $(BUILD_SYS_NAME) ($(BUILD_SVR_TYPE)), Built $(BUILD_DATE) by $(BUILD_USER)
export GHDL_VERSION = $(shell ghdl -v 2>&1 | head -n 1 | awk '{print $$1, $$2}')
export BUILD_STRING = $(PROJECT): $(GHDL_VERSION), ${BUILD_SYS_NAME} (${BUILD_SVR_TYPE}), Built ${BUILD_DATE} by ${BUILD_USER}

all: syntax

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2 changes: 2 additions & 0 deletions ethernet/ruckus.tcl
Original file line number Diff line number Diff line change
Expand Up @@ -14,4 +14,6 @@ if { $::env(VIVADO_VERSION) > 0.0} {
loadRuckusTcl "$::DIR_PATH/XlauiCore"
loadRuckusTcl "$::DIR_PATH/Caui4Core"
loadRuckusTcl "$::DIR_PATH/RoCEv2"
} else {
loadSource -lib surf -path "$::DIR_PATH/EthMacCore/rtl/EthMacPkg.vhd"
}
Original file line number Diff line number Diff line change
Expand Up @@ -21,29 +21,10 @@ use ieee.std_logic_1164.all;
-- arithmetic functions with signed or unsigned values
--use ieee.numeric_std.all;

entity chksum_tb is
end chksum_tb;

architecture behavior of chksum_tb is

-- component declaration for the unit under test (uut)

component chksum
port(
clk_i : in std_logic;
rst_i : in std_logic;
enable_i : in std_logic;
strobe_i : in std_logic;
length_i : in positive;
init_i : in std_logic_vector(15 downto 0);
data_i : in std_logic_vector(63 downto 0);
chksum_o : out std_logic_vector(15 downto 0);
--chksumreg_o : out std_logic_vector(15 downto 0);
valid_o : out std_logic;
check_o : out std_logic
);
end component;
entity RssiChksumTb is
end RssiChksumTb;

architecture behavior of RssiChksumTb is

--Inputs
signal clk_i : std_logic := '0';
Expand All @@ -65,19 +46,20 @@ architecture behavior of chksum_tb is
begin

-- Instantiate the Unit Under Test (UUT)
uut : Chksum port map (
clk_i => clk_i,
rst_i => rst_i,
enable_i => enable_i,
strobe_i => strobe_i,
init_i => init_i,
data_i => data_i,
chksum_o => chksum_o,
length_i => 3,
--chksumReg_o => chksumReg_o,
valid_o => valid_o,
check_o => check_o
);
uut : entity surf.RssiChksum
port map (
clk_i => clk_i,
rst_i => rst_i,
enable_i => enable_i,
strobe_i => strobe_i,
length_i => 3,
init_i => init_i,
data_i => data_i,
chksum_o => chksum_o,
--chksumReg_o => chksumReg_o,
valid_o => valid_o,
check_o => check_o
);

-- Clock process definitions
clk_i_process : process
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