Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments, allowing host compiled programs to run in a logic simulation. and drive a memory mapped bus
python c fpga cpp processor vhdl logic verification dpi verilog systemverilog pli vpi codesign simulation-element asic-verification logic-simulation dpi-c cosimulation vhpidirect
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Updated
Feb 6, 2026 - VHDL