[AMDGPU] Add machineFunctionInfo to recent MIR tests

[perlfu]

Initialize machineFunctionInfo in recently added MIR tests to assist in downstream testing.

[llvmbot]

@llvm/pr-subscribers-backend-amdgpu

Author: Carl Ritson (perlfu)

Changes

Initialize machineFunctionInfo in recently added MIR tests to assist in downstream testing.

---

Full diff: https://github.com/llvm/llvm-project/pull/179602.diff

2 Files Affected:

• (modified) llvm/test/CodeGen/AMDGPU/gfx11-sgpr-hazard-latency.mir (+2)
• (modified) llvm/test/CodeGen/AMDGPU/schedule-barrier-latency-gfx9.mir (+2)

diff --git a/llvm/test/CodeGen/AMDGPU/gfx11-sgpr-hazard-latency.mir b/llvm/test/CodeGen/AMDGPU/gfx11-sgpr-hazard-latency.mir
index f401d0b515373..9c433c7a139a8 100644
--- a/llvm/test/CodeGen/AMDGPU/gfx11-sgpr-hazard-latency.mir
+++ b/llvm/test/CodeGen/AMDGPU/gfx11-sgpr-hazard-latency.mir
@@ -5,6 +5,8 @@
 ---
 name:            gemm_loop1
 tracksRegLiveness: true
+machineFunctionInfo:
+  isEntryFunction: true
 body:             |
   ; GFX11-LABEL: name: gemm_loop1
   ; GFX11: bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/schedule-barrier-latency-gfx9.mir b/llvm/test/CodeGen/AMDGPU/schedule-barrier-latency-gfx9.mir
index 7be5b164cd1a1..eee018f0301e4 100644
--- a/llvm/test/CodeGen/AMDGPU/schedule-barrier-latency-gfx9.mir
+++ b/llvm/test/CodeGen/AMDGPU/schedule-barrier-latency-gfx9.mir
@@ -136,6 +136,8 @@
 ---
 name: test_workgroup
 tracksRegLiveness: true
+machineFunctionInfo:
+  isEntryFunction: true
 body: |
   bb.0:
     %0:sgpr_256 = IMPLICIT_DEF

[github-actions]

🐧 Linux x64 Test Results

• 189570 tests passed
• 5046 tests skipped

✅ The build succeeded and all tests passed.

[github-actions]

🪟 Windows x64 Test Results

• 130429 tests passed
• 2909 tests skipped

✅ The build succeeded and all tests passed.

[arsenm]

We really ought to add the calling convention to the generic function section